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<rant_on> Ya' know.. I was intrigued by these parts.. wondering if I could use them.. Even if I do have an ADC I still need some analog b4 it (get the level to the right stage of 0DBFS, Anti-Alias Filter etc - Unbalanced to Balanced conversion etc) So I decided to check these out.. No why the hell does Lattice make me register.. and turn my cookies back on before they will allow me to download a datasheet.. what the hell does it matter.. they make there $$$ selling chips not playing web games like many web companies.. This inconvenience to the customer is about enough to make me not consider using a chip that I probably have a good use for.. When will these companies get a clue.. give us too many hoops to jump and they will loose the customer. </rant_off> Hawker Steve Dewey wrote: > > Hi > > I was wondering : what is the point of the analogue FPGAs available from > Lattice and others, in the case where the signal processing finally > involves an ADC ? Bearing in mind the narrow frequency range (Filter > corner frequency from 50 kHz to 500 kHz for Lattice) is it not as easy > to have a 1 to 10 MHz ADC and do all your processing inside a general > digital FPGA that can be clocked at 100 MHz ? > > I know that there may be niche applications for these devices, but does > anyone out there see them ever making a big impact on the market ? > > Of course, the analogue die-hards will say that an analogue FPGA has > existed for over 25 years. It's called a quad op-amp and it's programmed > with those funny things called resistors and capacitors ;-) > > Cheers > > -- > Steve Dewey > steve at s-dewey dot demon dot co dot ukArticle: 26226
> > > Before I write the check > > > for this widget ($30K + 20% forever) I'd like to be sure it does > > > what I need. > > > > For $30k, call me and I'll do your floorplanning by hand ;-) > > For $30K are you willing to support the tool for the next five > years? Ok, I'm not either, but I get slipped some bananas under > the door too. ;-) Support the tools? Well, my hands, I am sure, will continue to work fine for the next 5 years. Want a quote for the bean-counters? Banana's in labs is a bad idea...unless you have a carpeted lab...Article: 26227
I don't like the games some companies play on their web sites either. But I deal with that by giving synthetic information. I have only found one that really verified the information. But none of them actually check to see if the person can be reached, etc. So just save your cookie file, then play their game with whatever info you care to give them. Then restore your cookie file back to the pre-vendor state. I know that it is a pita. But if they get enough of a lack of cooperation on their web site, they will realize that they are better off just not bothering. BTW, they are not doing this without a reason. Unlike some web sites that want your info so that they can sell it, semiconductor companies typically want to gather marketing info. This helps them figure out what products you are really interested in and what you are just curious about. Hawker wrote: > > <rant_on> > Ya' know.. I was intrigued by these parts.. wondering if I could use them.. > Even if I do have an ADC I still need some analog b4 it (get the level to the > right stage of 0DBFS, Anti-Alias Filter etc - Unbalanced to Balanced conversion > etc) So I decided to check these out.. > No why the hell does Lattice make me register.. and turn my cookies back on > before they will allow me to download a datasheet.. what the hell does it > matter.. > they make there $$$ selling chips not playing web games like many web > companies.. > This inconvenience to the customer is about enough to make me not consider using > a chip that I probably have a good use for.. > When will these companies get a clue.. give us too many hoops to jump and they > will loose the customer. > </rant_off> > > Hawker -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26228
rickman wrote: > BTW, they are not doing this without a reason. Unlike some web sites > that want your info so that they can sell it, semiconductor companies > typically want to gather marketing info. This helps them figure out what > products you are really interested in and what you are just curious > about. > Doesn't my orders to Future, Marshall, Insight, etc tell them that so much more accurately than any web shenanigans? Seems that is what the field reps are for as well. Seems to me if I download a PDF because it looks interesting, or I download a PDF because I have an actual need an interest in the part they couldn't get accurate info... They can track where I go easily enough (and what I download) without a cookie or registration. Any web stats program will give them that I to give most of these fake names etc... but I'm rapidly getting tired of playing games.... and games like my e-mail address (a News only one to keep the Spammers outa my work account). I had one earlier today were I couldn't download a software patch unless I downloaded there custom on-line e-mail program (which was a netscape plug-in). That one took the cake. I didn't need the online account.. just the software patch to an unrelated program! HawkerArticle: 26229
Rickman,
Lattice is going a little bit farther than most semiconductor
companies.
When you fill out all that garbage to get into their web site, it DOES
go somewhere! It goes to many places, but one very important place it goes
to, as far as you are concerned, is the local sales office. They get a
printout of everything you wrote. Do not be surprised if a salesperson
calls you nonchalantly just asking how you are doing, what are you working
on, etc., etc. This guy or gal has a rap sheet on you a mile long, and he
knows exactly what you entered into the web site along with other
information gleaned by FAEs and sales people. These sales people may be
distributor FAEs, manufacturer's reps, or actual Lattice reps. The info is
compiled all into one or several databases, and the local guys have access
to the data.
You might want to play along with his nonchalant approach and then ask
him where he got his information.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:39E200CC.E9F08436@yahoo.com...
> I don't like the games some companies play on their web sites either.
> But I deal with that by giving synthetic information. I have only found
> one that really verified the information. But none of them actually
> check to see if the person can be reached, etc. So just save your cookie
> file, then play their game with whatever info you care to give them.
> Then restore your cookie file back to the pre-vendor state.
>
> I know that it is a pita. But if they get enough of a lack of
> cooperation on their web site, they will realize that they are better
> off just not bothering.
>
> BTW, they are not doing this without a reason. Unlike some web sites
> that want your info so that they can sell it, semiconductor companies
> typically want to gather marketing info. This helps them figure out what
> products you are really interested in and what you are just curious
> about.
Article: 26230Hawker wrote: > > <rant_on> > Ya' know.. I was intrigued by these parts.. wondering if I could use them.. > Even if I do have an ADC I still need some analog b4 it (get the level to the > right stage of 0DBFS, Anti-Alias Filter etc - Unbalanced to Balanced conversion > etc) So I decided to check these out.. > No why the hell does Lattice make me register.. and turn my cookies back on > before they will allow me to download a datasheet.. what the hell does it > matter.. > they make there $$$ selling chips not playing web games like many web > companies.. > This inconvenience to the customer is about enough to make me not consider using > a chip that I probably have a good use for.. > When will these companies get a clue.. give us too many hoops to jump and they > will loose the customer. > </rant_off> Did you send them an e-mail, complaining about their policies? Did you spell- and grammar-check it? (For example, you don't _loose_ the customer, you _lose_ him.) Also, you can get software that lets you block/accept cookies based on the domain. These cookie-blockers will also let you dump the cookies at the end of a session. As an example, I block cookies from almost all "consumer" sites (and if they require registration, I leave), but I imagine that semiconductor companies aren't looking to harvest your e-mail address for spammers, so it's not as big a deal as you make it out to be. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26231
Bob Perlman wrote:
>
> Hi -
>
> I just have to know--what is Long Island Verilog? Is it to Verilog
> what Long Island iced tea is to iced tea, i.e., vaguely similar in
> appearance but more intoxicating? Is there a reference manual?
Nawww, it's Verilog with a funny accent ("veer-ih-lawg").
-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u
Article: 26232Rick Filipkiewicz wrote: > > Andy Peters wrote: > > > brian13074@my-deja.com wrote: > > > > > > (Project Leader, Architecture Modeling) > > > > > > I'm a headhunter who specializes in Engineering, > > > ASIC, ATM and related fields. > > > > > > I currently have opportunities available for ASIC Design Engineer > > > professionals with a dynamic company. > > > > [snip all the other stuff] > > > > Last I checked, this newsgroup was called comp.arch.fpga. Dig? > > > > Isn't it amazing how few static companies full of amateurs there are ? That's only rivalled by how few headhunters have clues. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26233
Bob, The new 158 makes reference to some AVX caps. Its your choice: Z5U, X7R, Y5U materials or families. Made by all ceramic cap vendors. I did telecom design for 20 years, so I liked X7R for their stability over temperature. Just make sure you pick something that has a really nice impedance dip (closer to 0 ohms) around your frequency (not required, but definitely helps). No special multi-ball footprinted caps are required. Just the plain 1206, 804, or smaller SM caps are just fine. I like to also have a couple of lo esr aluminum electrolytics, or tanatalums around for the low frequency stuff. They can go anywhere (at least 1000uF). You can call it overkill, but I always passed FCC Part 15, Bellcore NEBS, or VDE. Oh, the systems worked, as well. Yes, there were a lot of other things that went into passing through the requirements needle, but the emissions from a poorly bypassed board can be a real issue, followed by poor signal integrity from mis-matched impedances, and lack of impedance controlled PCB design. Spartan II, since it is a derivative of the Virtex family, is pretty much the same animal. The core transistors got smaller, so the currents there are balanced by them getting smaller and a little faster, but the process isn't push to scream, so its a wash. The IO transistors can't get smaller, as they have to meet the IO standards, so you have the same behavior there as well. The Spartan II folks are working on support collaterial specific to their products, but they can piggy back off the classic Virtex support docs for awhile. If you have a specific Spartan II question, please use my Xilinx email, austin@xilinx.com Austin Bob Baman wrote: > Austin, > > Just curious - will there be any specific references to decoupling caps for > BGA parts in the revision of XAPP158? This info would be very pertinent to > the Spartan II design I am wrapping up. > > Regards, > > Bob Bauman > Lynx Studio Technology > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:39D25202.7DECA224@xilinx.com... > Martin, > In our appnote 158 (re-write due to be released perhaps this week), we make > a point of recommending a number of large capacitors precisely because we > don't know what the frequency distribution is, and you probably are not sure > either. > AustinArticle: 26234
Neil Franklin wrote: > But these are those who may make FPGAs their > next (or after next) job, when they get fed up with writing yet another > web application. Stop right there. You're thinking that a software person can design hardware? Sorry. Just because VHDL is a "programming language," it doesn't mean that a person who writes VHDL is a good hardware designer. There's a WHOLE LOT MORE to FPGA design -- and hardware design in general -- than just writing code. BTW: I write pretty crappy C code. I let the software guys do it. > Bitstream format? How are them bits scattered to the controlling SRAMs > in the chip? Synplicity has to know this to create bitstreams. This is > the equivalent of knowing the 80x86 code to write an C compiler (which > Intel publishes). Synplicity does NOT know the bitstreams, nor does it need to. Their synthesis tool spits out a netlist, which the (Xilinx-proprietary) mapper, placer and router turn into a bitstream. > For hobbyist time != bucks. And for newbies, they will have to learn > some tool and chip anyway. For the professional, time certainly equals bucks. And I can't afford to use hobbyist-level tools. > The gvhdl projects back end writer may need help (just like the gcc > 80x86 back end writer), but that would be no different for Xilinx than > if the Synpicity back end writer having problems. Why hasn't anyone written a gvhdl-type of synthesis tool? The chip vendors all published very detailed architectural descriptions. The schematic-capture-based designers use that information to "synthesize" the netlist by directly drawing and connecting the components. > A far more important boon will be drawing in lots of self-taught new > programmers, who will naturally use FPGAs to solve problems. Just look > at the embedded Linux guys (MP3 Players, set top boxes, Cobalt > Qube). Again, hardware design isn't as "simple" as you make it out to be. I've seen the results of what "alleged" hardware designers can do with FPGAs, Senator, and I'm here today to tell you that it ain't pretty. > Anyone who can learn C can learn VHDL. ARRRGH! > FPGAs are really just an > type of highly parallel CPU, with the program distributed over chip > space, not over execution time. Um, no. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26235
Neil Franklin wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > > The bitstream can be reverse engineered, or actually there is no need > > for a bitstream format just to translate VHDL to a FPGA. The > > intermediate format is EDIF > > What is that? I have not seen that mentioned yet. FPGA newbie, as I said :-). EDIF (and also the Xilinx XNF) is an ASCII netlist file. It can be generated by two tools: 1) the synthesis tool, which translates the VHDL or Verilog into a (hopefully-optimized) netlist, or 2) if you do your design with schematics, the schematic capture tool can spit out a netlist. The details the chip's architectural features and primitives and the interconnects between them. > Is there a good web page that details the various tools, steps, > intermediate files used in FPGA development? http://www.xilinx.com/ http://www.altera.com/ http://www.actel.com/ http://www.quicklogic.com/ who'd I miss? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26236
Phil Hays wrote: > 2) -Pro produces better results than the regular Synplify. Just curious: How so? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26237
Hawker wrote: > rickman wrote: > > BTW, they are not doing this without a reason. Unlike some web sites > > that want your info so that they can sell it, semiconductor companies > > typically want to gather marketing info. This helps them figure out what > > products you are really interested in and what you are just curious > > about. > > > > Doesn't my orders to Future, Marshall, Insight, etc tell them that > so much more accurately than any web shenanigans? No, not mine anyway, as I cannot order what is not available. > > Seems that is what the field reps are for as well. > Seems to me if I download a PDF because it looks interesting, > or I download a PDF because I have an actual need an interest in the > part they couldn't get accurate info... They can track where I go > easily enough (and what I download) without a cookie or registration. > Any web stats program will give them that > > I to give most of these fake names etc... but I'm rapidly getting tired > of playing games.... and games like my e-mail address (a News only one > to keep the Spammers outa my work account). I had one earlier today > were I couldn't download a software patch unless I downloaded there > custom on-line e-mail program (which was a netscape plug-in). > That one took the cake. I didn't need the online account.. just > the software patch to an unrelated program! > > HawkerArticle: 26238
On Sat, 7 Oct 2000 22:24:32 +0200, "Domagoj" <domagoj@engineer.com> wrote: > Thanks. But I meant of more subtle things, that might make problems >in vhdl parsing. For example : if there are two subprograms with the same >signature visible within some architecture, Ashenden states that >neither one of them is visible. On the other side, some simulator >manuals state that if there are two subprograms with the same signature, >some programs prefer the explicit one (if another is implicit). I didn't >understand that one pricesly. The manual stated that this case is found >in practise. I wanted to know what other deviations from LRM could >be find in practise. True enough. Synopsys incorrectly handles this case (the explicit declaration is visible), and some other compilers have a flag to copy this incorrect behaviour. Have a look at: http://www.model.com/support/technote/tnsynopsys.html This appnote covers the 'explicit' case and a couple of other problem areas that may be interesting. I wouldn't worry about this too much though - you're only trying to copy the known incorrect behaviour of other compilers. This is exactly what Leapfrog's compatibility flag does, so you might want to copy the flag directly. EvanArticle: 26239
Maciek, Rotem is right. This is a known issue. Please open the case with Xilinx hotline or contact your FAE to get the patch. Regards, Yenni gazit@my-deja.com wrote: > Maciek, > There is a known compatibility problem of SRP3 and localized OS. > We just got the patch (some XML files from Xilinx)for our Hebrew > enabled Windows. > You should contact your local FAE about that. > > Good luck, > Rotem Gazit. > > In article <39DD975A.925549F5@fuw.edu.pl>, > Maciek Kudla <kudla@fuw.edu.pl> wrote: > > After installation sp3 for Foundation 3.1 (Win98) I can not implement > > any vhdl code. > > Project menager stops with following message: > > *** > > Reading component libraries for design expansion... > > Annotating constraints to design from file "race.ucf" ... > > Checking timing specifications ... > > Checking expanded design ... > > The XML Parser environment is incorrectly set up, preventing it from > > finding its text transcoding files. Normally these will be located > > via the ICU_DATA environment variable, or located relative to the > > XML4C2 DLL (or SharedLib.) Please check your installation > > *** > > Sombody knows what it is? > > > > Maciek > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 26240
does anybody know where can I find the VHDL model of Motorola 68000 processor for educational use? Thanks --ATArticle: 26241
Andy Peters wrote: > > Neil Franklin wrote: > > Is there a good web page that details the various tools, steps, > > intermediate files used in FPGA development? > > http://www.xilinx.com/ > http://www.altera.com/ > http://www.actel.com/ > http://www.quicklogic.com/ > > who'd I miss? You should have left out all of these. He asked for a *good* web page, not these. If you are trying to learn the basics of FPGA design, especially the tools, I can think of no worse place than the vendors web sites. Perhaps I should not generalize so much. I know that Xilinx is not very newbie friendly. I can't say anything about Altera, Actel or Quicklogic. But while we are on the topic of alternative tools for hardware design. It has occurred to me that you could do a fairly decent job of describing a netlist using a language like Forth. I picture it working more like a hierarchical schematic and less like an HDL like Verilog or VHDL. Anyone considered something like this? I know that Chuck Moore does full ASIC design in Forth. But then I don't know that I would do everything the way Chuck Moore does. Anyone have an opinion? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26242
In article <39E1B7BB.FBC3E6AE@tu-harburg.de>, Marc Reinert <reinert@tu-harburg.de> wrote: > rotemg@mysticom.com schrieb: > > > After changing the line in the UT file to: > > > > "-g StartUpClk:JTAGCLK" > > > > You should run bitgen again. > > for example: > > "bitgen design_name.ncd -l -f ut_file_name.ut design_name_jtag.bit" > > > > I get the following errormessage: > > "ERROR:Bitgen:42 - Unknown setting "JTAGCLOCK" for option "StartupClk". > Please > consult the "BitGen" Section in Chapter Twelve of the Development System > > Reference Guide for the appropriate command-line options to create a > bitstream file or consult the "Implementation Options" Section of the > Design > Manager/Flow Engine Reference/User Guide for Configuration Template > Settings. > > ERROR:Bitgen:112 - OutputsActive must be UserClk 2, DI, DI+1, or DI+2 when > StartupClk is UserClk and SyncToDone is Yes. > ERROR:Bitgen:113 - GSRInactive must be UserClk 2, DI, DI+1, or DI+2 when > StartupClk is UserClk and SyncToDone is Yes. > ERROR:Bitgen:157 - Bitgen will terminate because of the above errors." > > The same for "JTAGCLK"! > > Marc > > opps, Taking a closer look I see you are using 4K device. The information I gave is correct.... for Virtex/Spartan II. Sorry for miss leading you. Rotem. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26243
"Anurag Tiwari" <atiwari@cs.wright.edu> wrote > does anybody know where can I find the VHDL model of Motorola 68000 > processor for educational use? I don't. But here are two sites describing commercial ones. Sierra Circuit Design http://www.teleport.com/~scd/avail_ip.htm Digital Core Designs D68000 http://www.dcd.com.pl/english/d68000.htm Perhaps Motorola has something. They should. Please let us know if something turns up. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 26244
This may sound like a dumb question, but is the starter version of ModelSim XE speed crippled above a certain design size? I have been increasing the size of my testbench and all of a sudden the simulation slowed to a crawl. It had been running very nicely simulating about 1 us of simulation time in 2 secs. Now it take about 20 or 30 secs for the same amount of simulation. At first I thought it was something in my code like an infinite loop or other very inefficient construct. But I can get it to speed up by cutting out code (about 10 lines) regarless of where I cut it out. When I simulate the full size design, I get a message that says, "# WARNING: Design size of 513 statements exceeds ModelSim XE-Starter recommended capacity." Am I correct in assuming that this is an intentional limit that they put in to encourage you to buy the upgraded tools? They don't make it very easy to figure this out, nor do they make it easy to get info on what it takes to upgrade. I could not find a link to their web page anywhere. The "About" box points you to Xilinx. I guess they are afraid of support calls. Of course I found a web page by searching on their name. But they don't give info on the "starter" package or about a direct upgrade. Anyone know if there is a simple upgrade to unlock the speed governor? Or do you just buy ModelSim XE full package? Anyone know what it costs? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26245
Thanks a lot ! Exactly what I was looking for..... Any
other cases ?
regards,
-------------------------------------------
- Domagoj -
- Domagoj@engineer.com -
-------------------------------------------
<eml@riverside-machines.com.NOSPAM> wrote in message
news:39e22aaa.2610087@news.dial.pipex.com...
> On Sat, 7 Oct 2000 22:24:32 +0200, "Domagoj" <domagoj@engineer.com>
> wrote:
>
> > Thanks. But I meant of more subtle things, that might make problems
> >in vhdl parsing. For example : if there are two subprograms with the same
> >signature visible within some architecture, Ashenden states that
> >neither one of them is visible. On the other side, some simulator
> >manuals state that if there are two subprograms with the same signature,
> >some programs prefer the explicit one (if another is implicit). I didn't
> >understand that one pricesly. The manual stated that this case is found
> >in practise. I wanted to know what other deviations from LRM could
> >be find in practise.
>
> True enough. Synopsys incorrectly handles this case (the explicit
> declaration is visible), and some other compilers have a flag to copy
> this incorrect behaviour. Have a look at:
>
> http://www.model.com/support/technote/tnsynopsys.html
>
> This appnote covers the 'explicit' case and a couple of other problem
> areas that may be interesting. I wouldn't worry about this too much
> though - you're only trying to copy the known incorrect behaviour of
> other compilers. This is exactly what Leapfrog's compatibility flag
> does, so you might want to copy the flag directly.
>
> Evan
Article: 26246> Neil Franklin wrote: > > But these are those who may make FPGAs their > > next (or after next) job, when they get fed up with writing yet another > > web application. Andy Peters <"apeters <"@> n o a o [.] e d u> writes: > Stop right there. You're thinking that a software person can design > hardware? Sorry. Just because VHDL is a "programming language," it > doesn't mean that a person who writes VHDL is a good hardware designer. If I'm not mistaken, VHDL *isn't* a programming language. It's a "Hardware Description Language". the purpose of VHDL is not to program anything; you're not telling some CPU what to do, you're describing a hardware construct. Just like a netlist isn't a programming language, HTML isn't a programming language, (The 'M' doesn't stand for Programming!), SVF (Serial Vector Format) isn't a programming language. > > Bitstream format? How are them bits scattered to the controlling SRAMs > > in the chip? Synplicity has to know this to create bitstreams. This is > > the equivalent of knowing the 80x86 code to write an C compiler (which > > Intel That doesn't really translate, i'm afraid. FPGA's and CPU's are fifferent animals, they are. > > Anyone who can learn C can learn VHDL. > > ARRRGH! <shrug> You're probably right there. But anybody that can learn C can learn electronics, too. And spanish. > > FPGAs are really just an > > type of highly parallel CPU, with the program distributed over chip > > space, not over execution time. Yup. FPGAs are *just like* CPU's. 'cept they're not 'central' and they don't 'process'. They *are* units, though. Saying an FPGA is like a CPU is the same as taking a whole pile of 74HCxx series chips in your left hand and calling *it* a CPU. Or pieces of Lego! Until you *make* something with it, it's still nothing. -kentArticle: 26247
A year or two ago, I went and visited the Lattice Site. The very same day, I got a call from the Lattice sales guy, asking me if I found what I was looking for on their Web site that day. How did he know I was at their site that day? Could it be the cookies? Bob S. In article <39E1FE4C.F5255B3B@connriver.net>, Hawker <Hawker@connriver.net> wrote: > > <rant_on> > Ya' know.. I was intrigued by these parts.. wondering if I could use them.. > Even if I do have an ADC I still need some analog b4 it (get the level to the > right stage of 0DBFS, Anti-Alias Filter etc - Unbalanced to Balanced conversion > etc) So I decided to check these out.. > No why the hell does Lattice make me register.. and turn my cookies back on > before they will allow me to download a datasheet.. what the hell does it > matter.. > they make there $$$ selling chips not playing web games like many web > companies.. > This inconvenience to the customer is about enough to make me not consider using > a chip that I probably have a good use for.. > When will these companies get a clue.. give us too many hoops to jump and they > will loose the customer. > </rant_off> > > Hawker > > Steve Dewey wrote: > > > > Hi > > > > I was wondering : what is the point of the analogue FPGAs available from > > Lattice and others, in the case where the signal processing finally > > involves an ADC ? Bearing in mind the narrow frequency range (Filter > > corner frequency from 50 kHz to 500 kHz for Lattice) is it not as easy > > to have a 1 to 10 MHz ADC and do all your processing inside a general > > digital FPGA that can be clocked at 100 MHz ? > > > > I know that there may be niche applications for these devices, but does > > anyone out there see them ever making a big impact on the market ? > > > > Of course, the analogue die-hards will say that an analogue FPGA has > > existed for over 25 years. It's called a quad op-amp and it's programmed > > with those funny things called resistors and capacitors ;-) > > > > Cheers > > > > -- > > Steve Dewey > > steve at s-dewey dot demon dot co dot uk > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26248
Rick, Check out http://www.xilinx.com/products/software/mxe.htm#products At this site, it says the XE version slows down at 8000 lines of code, and the XE starter is appropriate for designs less than 500 lines. Last I looked, the full XE edition cost $995 I believe for a year. Hope this helps, Bob In article <39E24FF1.A0B2EA3E@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > This may sound like a dumb question, but is the starter version of > ModelSim XE speed crippled above a certain design size? > > I have been increasing the size of my testbench and all of a sudden the > simulation slowed to a crawl. It had been running very nicely simulating > about 1 us of simulation time in 2 secs. Now it take about 20 or 30 secs > for the same amount of simulation. > > At first I thought it was something in my code like an infinite loop or > other very inefficient construct. But I can get it to speed up by > cutting out code (about 10 lines) regarless of where I cut it out. When > I simulate the full size design, I get a message that says, > "# WARNING: Design size of 513 statements exceeds ModelSim XE-Starter > recommended capacity." > > Am I correct in assuming that this is an intentional limit that they put > in to encourage you to buy the upgraded tools? They don't make it very > easy to figure this out, nor do they make it easy to get info on what it > takes to upgrade. I could not find a link to their web page anywhere. > The "About" box points you to Xilinx. I guess they are afraid of support > calls. > > Of course I found a web page by searching on their name. But they don't > give info on the "starter" package or about a direct upgrade. > > Anyone know if there is a simple upgrade to unlock the speed governor? > Or do you just buy ModelSim XE full package? Anyone know what it costs? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26249
On Tue, 10 Oct 2000 00:49:34, Kent Orthner <korthner@hotmail.nospam.com> wrote: > > > > > > Neil Franklin wrote: > > > But these are those who may make FPGAs their > > > next (or after next) job, when they get fed up with writing yet another > > > web application. > > Andy Peters <"apeters <"@> n o a o [.] e d u> writes: > > Stop right there. You're thinking that a software person can design > > hardware? Sorry. Just because VHDL is a "programming language," it > > doesn't mean that a person who writes VHDL is a good hardware designer. > > If I'm not mistaken, VHDL *isn't* a programming language. It's a "Hardware > Description Language". the purpose of VHDL is not to program anything; you're > not telling some CPU what to do, you're describing a hardware construct. Well, it is a programming language. The intention is certainly to abstract hardware, but it is a programming language. The interesting thing about VHDL and Verilog (remember I'm a relative newbie here) is the concurrancy. Things one learns in "programming" simply don't work when things happen concurrenty. Trust me. This is not the only divide I see between "programming" and "HDL". There are the details of synthisis, which has little to do with the language. This invloves telling the tool what you want, regardless of what the authors of the toll think you want. Also, you forget the fact that Engineers have things like timings to meet, and the I/O is not a monitor. > Just like a netlist isn't a programming language, HTML isn't a programming > language, (The 'M' doesn't stand for Programming!), SVF (Serial Vector Format) > isn't a programming language. Hmm, VHDL doesn't seem to me to have any of the above atributes. Sure, you can code hardware in VHDL as if it's a schematic (i.e. a markup language), but trust me. you soon learn that isn't the way to go. HDLs are a very different beast. I've found (any) assembler trivial by comparison. > > > Bitstream format? How are them bits scattered to the controlling SRAMs > > > in the chip? Synplicity has to know this to create bitstreams. This is > > > the equivalent of knowing the 80x86 code to write an C compiler (which > > > Intel > > That doesn't really translate, i'm afraid. FPGA's and CPU's are fifferent > animals, they are. That they be. Who cares about the bits. I certainly don't, but would like to be able to do partial loads. Better docs would always be welcomed! > > > > Anyone who can learn C can learn VHDL. > > > > ARRRGH! > <shrug> You're probably right there. But anybody that can learn C can > learn electronics, too. And spanish. Good grief. You are a nut! ...or are you a troll? No matter, you are *so* wrong! > > > FPGAs are really just an > > > type of highly parallel CPU, with the program distributed over chip > > > space, not over execution time. > > Yup. FPGAs are *just like* CPU's. 'cept they're not 'central' and they > don't 'process'. They *are* units, though. Saying an FPGA is like a CPU > is the same as taking a whole pile of 74HCxx series chips in your left > hand and calling *it* a CPU. Or pieces of Lego! Until you *make* > something with it, it's still nothing. Well, I see you have experience on "nothing". Sorry, but you have not the first clue how to get to first base! I think it's rather arrogant for a "C programmer" to think they understand hardware. "C programmers" don't need to know about concurrancy, and if you did you would sh!t. ...and that's only the start of your problems. ..sorry folks. I'm a relative newbie to programmable logic, but have been a design engineer for 25+ years (mostly systems stuff though). This article just torqued me off, knowing what I've gone through this year... The flat-out arrogance! ..ok I'll go bac to (mostly) lurking. ---- Keith
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