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Messages from 26625

Article: 26625
Subject: Re: UCF Question
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 23 Oct 2000 09:42:42 +0200
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:

> Magnus Homann wrote:
> > I have to admit that it might not be very common to do this kind of
> > design. Unless you are into gigabit ethernet! Transmit path, on the
> > most common devices, is 10 bit @ 125MHz, and receive path is 10 bit
> > clocked with two 62.5 MHz clocks at 180 degrees (positive edge). So
> > you have one transmit and two receive clocks. The delay between
> > positive edges of the different receive clocks is 7.5 to 8.5 ns. Data
> > valid (on receive) is 3 ns before and 2 ns after [1], and in an
> > FPGA you'd preferrably take the PAD to two different FFs, perhaps one in
> > the IOB.
> 
> To make sure I understand what you are saying, there are four data
> inputs with dual clocks of opposite phases. So you have four clocks at a
> similar phase

Nah, not really, they are totally unrelated. Doesn't matter for your later suggestion, though.

> and there are four clocks that are 180 degrees out,
> essentially inverted. You are saying that the clocks vary from 7.5 to
> 8.5 nS from pos edge of "non-inverted" clock to pos edge of "inverted"
> clock. 
 
> If the skew is only 1 nS total (+- 0.5 nS) and you have 2 nS hold time,
> why can't you use one clock for both data phases of a given input? This
> would reduce your setup and hold to 2.5 nS and 1.5 nS, respectively. I
> believe this will work in a fast FPGA. 

I could have done that, as you said. I thought about it and chose not
to, I can't remember why. Perhaps the numbers were a bit more
"negative". Anyway, you'd still have two FFs for each PAD, and that
might have been the problem.

> > Now, I had to [2] fit four(4) of those interfaces in one FPGA, so it
> > makes 2*4 =8 receive clocks, but I used the same transmit clock, so
> > "only" 9 pretty fast clocks were needed. The FPGA I used had four
> > global clocks, and four "fast" inputs, ergo I had to use one
> > non-decicated input.
> ...snip...
> > Thanks you for listening to my rant!
> > 
> > [1] AMCC S2060
> > [2] Nobody forced me, but it was an interesting challenge.
> > [3] Consider where you have 8 bits and a clock going out of your
> >     FPGA and 1 meter across the backplane. The signals are all of the same
> >     length, and you run say 200 Mbaud. Skew at ouput is important, but
> >     actual delay is not.
> 
> I agree that this will become more common, but that does not solve the
> problems of building a chip to meet the spec.
> In these chips, the skew
> is an undocumented parameter as it depends greatly on the routing as
> well as the chip fabrication. It might be something that Xilinx will
> consider documenting in the future for global clocks and IOBs. 

The problems of building the chipp is up to the manufacturer. I
believe that it is not that complicated to take these things into
account. For minimum delay, a very "safe" estimate would get you quite
far. For max delay every ps counts, as that's what marketing
demands. Not so on min delay. For instance, your "25% of max" would be
a very good number to guarantee, but even _to be able to constrain_ would be a step forward.

It's not a technical problem, is a lack of understanding of the need, IMHO.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 26626
Subject: Re: PCB's for re-casting the form factor of a QFP
From: "Mike H." <mikeh@spamlessimageproc.com>
Date: Mon, 23 Oct 2000 12:46:55 +0100
Links: << >>  << T >>  << A >>

"Rob Finch" <robfinch@sympatico.ca> wrote in message
news:KJQI5.367948$Gh.11163508@news20.bellglobal.com...
> Does anyone make little printed circuit boards whose only purpose is to
> bring out the signals from a quad flat pack so that wire wrap pins or
> headers can be attached for wire wrapping? (eg 160QFP => 8x20 pins) I'm
> willing to solder the parts together myself. I'm just looking for the PCB (a
> $20 solution) not a $500 adapter.

http://www.emulationtechnology.com

also

http://www.winslow.co.uk

I can't guarantee a $20 solution though.....


MH




Article: 26627
Subject: Typical toggle rates for power estimation ...
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 23 Oct 2000 14:26:20 +0200
Links: << >>  << T >>  << A >>
Hello,

I would like to estimate the power dissipation using the "virtex power
estimator" provided by Xilinx. Hoewever, i have some question regarding
typical values for the toggle rate. 

Although Xilinx application note states that toggle rate is usually
between 6 and 12% for most designs, it seems very low to me (my designs
consists of heavily pipelined floating point MACS). 

Would anyone have references about typical toggle rate values (I'm not
sure how application dependant are these figures, so even upper bound
value* would be a good start)

* Yes, I know that 100% is an upper bound value :)

Thanks

Steven

Article: 26628
Subject: SV: PCB's for re-casting the form factor of a QFP
From: "Daniel Nilsson" <danielnilsson@REMOVE_THIShem3.passagen.se>
Date: Mon, 23 Oct 2000 14:46:26 +0200
Links: << >>  << T >>  << A >>
I have the same problem myself. I want to use 2.54*2.54 mm prototype board
and use one pqfp-240, one pqfp-100 and some plcc-84. Since I can't find any
adapter fitting my needs and budget I will probably have to design this
myself.



Article: 26629
Subject: How secure from pirates is a Quick Logic part ?
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Mon, 23 Oct 2000 12:53:06 GMT
Links: << >>  << T >>  << A >>
Hello,

What level of effort is required to copy a Quick Logic part ?

Dan



Article: 26630
Subject: Re: SV: PCB's for re-casting the form factor of a QFP
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 23 Oct 2000 09:07:26 -0400
Links: << >>  << T >>  << A >>
> I have the same problem myself. I want to use 2.54*2.54 mm prototype board
> and use one pqfp-240, one pqfp-100 and some plcc-84. Since I can't find any
> adapter fitting my needs and budget I will probably have to design this
> myself.

You might consider the Aries Correct-a-Chip product line for converting PLCCs
and QFPs to a form more suitable for prototyping.  But the biggest QFP I see in
their list is 160 pins.  The company web site is www.arieselec.com.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 26631
Subject: RS422 interfacing to a FPGA ?
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Mon, 23 Oct 2000 13:41:54 GMT
Links: << >>  << T >>  << A >>
Hello,

I need to interface a digital camera to a Xilinx FPGA.
 (SMD-1M15  http://www.smd.com/products/1M15.asp)

The camera outputs its clock and pixel data as RS422. How do I convert this
to something the FPGA can input ?

Dan




Article: 26632
Subject: log2 function in VHDL
From: "Peter Lang" <Peter.Lang@rmvmachinevision.de>
Date: Mon, 23 Oct 2000 15:48:43 +0200
Links: << >>  << T >>  << A >>
Hi,
I am doing my first steps in VHDL.
I wanted to implement a log2-function using
Xilinx Foundation 3.1i with Synopsis FPGA Express 3.4.
I tried the following source-code, which I found here in the newsgroup.
But the Compiler found an error

Dpm: Error: Non-static loop or event waits in only some branches detected

I have no idea whats wrong.


package MATH is
   function log2 ( num : integer) return integer;
end MATH;

package body MATH is
  function log2 ( num : integer) return integer is
    variable diviser : integer;                           -- Divided to form
result
    variable acc     : integer;                             -- accumulates
result
  begin
    diviser := num;
    acc := 0;
    LogLoop : while (diviser >= 2) loop
      diviser := diviser / 2;
      acc     := acc + 1;
    end loop LogLoop;
    return acc;
  end function log2;
end MATH;





Article: 26633
Subject: Re: Typical toggle rates for power estimation ...
From: Ray Andraka <ray@andraka.com>
Date: Mon, 23 Oct 2000 13:50:36 GMT
Links: << >>  << T >>  << A >>
Actually, 50% is for practical purposes an upperbound if you assume random
states from cycle to cycle.  When you put real data through the system, this can
be reduced considerably, as the real data tends to be correlated from sample to
sample.  The opposite might be true if you have two interleaved data streams
going through the same logic.

Steven Derrien wrote:
> 
> Hello,
> 
> I would like to estimate the power dissipation using the "virtex power
> estimator" provided by Xilinx. Hoewever, i have some question regarding
> typical values for the toggle rate.
> 
> Although Xilinx application note states that toggle rate is usually
> between 6 and 12% for most designs, it seems very low to me (my designs
> consists of heavily pipelined floating point MACS).
> 
> Would anyone have references about typical toggle rate values (I'm not
> sure how application dependant are these figures, so even upper bound
> value* would be a good start)
> 
> * Yes, I know that 100% is an upper bound value :)
> 
> Thanks
> 
> Steven

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26634
Subject: Re: Typical toggle rates for power estimation ...
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 23 Oct 2000 16:00:25 +0200
Links: << >>  << T >>  << A >>


Ray Andraka wrote:
> 
> Actually, 50% is for practical purposes an upperbound if you assume random
> states from cycle to cycle.  When you put real data through the system, this can
> be reduced considerably, 

To what kind of values ? 12 % 25 % ?

> as the real data tends to be correlated from sample to
> sample.  The opposite might be true if you have two interleaved data streams
> going through the same logic.

So, as far as i understand, this rate is VERY application dependent.

Thanks

Steven

> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

Article: 26635
Subject: Re: Very Lucrative FPGA Jobs
From: "Austin Franklin" <austin@dark88room.com>
Date: 23 Oct 2000 14:11:32 GMT
Links: << >>  << T >>  << A >>


> The sad thing is, if he actually finds someone for this
> job (even though he didn't even say where the job is) he
> will make a 25% to 33% commission.

The realtors of the Engineering community...  Same two qualities.



Article: 26636
Subject: Atmel FPGA tools (was Re: Cheapy FPGA sw)
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Mon, 23 Oct 2000 16:32:56 +0200
Links: << >>  << T >>  << A >>
> Hi all,
>
> Is there any entry level tools for fpgas
> such as atmel at40k05?
>
> The free IDS6 tool from atmel is a bit
> too crappy. I don't mind buying a tool,
> but the budget isn't open ended...
>
> --
> *******************************************
> *   Russell Shaw, B.Eng, M.Eng(Research)  *
> *      email: russell@webaxs.net          *
> *      Victoria, Australia                *
> *******************************************

You might want to look at the FPSLIC toolset.
It aint free, costs $2800 but includes a number of goodies.
1) Mentor Modelsim VHDL/Verilog simulator.
2) Mentor Leonardo synthesis
3) Seamless coverification tool with an Atmel AVR model included.
    (If you buy this lot on a workstation , you pay around $125k ...)
4) Place & Route is still Figaro = IDS 7.x
    Most people make their complaint on the synthesizer.


You can test the toolset by buying the new FPSLIC demoboard.
Will only set you back half a k$ and has a time limited license. (4 months I
believe)
You can then subscribe for about $1k/year OR you can write FPSLIC
application notes. Any such appnote approved by Atmel will delay expiration
by 6 months....

--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

"Russ.Shaw" <russell@webaxs.net> wrote in message
news:39F19F96.1AB2E11C@webaxs.net...



Article: 26637
Subject: Re: xilinx floor planner issues
From: steve (Steve Rencontre)
Date: Mon, 23 Oct 2000 15:38 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <39F329BB.2D9397E1@andraka.com>, ray@andraka.com (Ray Andraka) 
wrote:

> Back annotation is sending data (generally timing data) backwards 
> through the
> tools flow to get improved performance based on the actual place and 
> route
> solution.  It is usually used in the context of timing simulations, in 
> which
> case the placed and routed timing results are passed back to the 
> simulator to
> get accurate timing numbers in the simulation (note these are generally 
> just
> worst case maximimum  delays, so be careful using them).
> 
> 
> erika_uk@my-deja.com wrote:
> > 
> > Hi,
> > 
> > could someone explain me what BACK ANNOTATION stands for ?
> > 
> > not just in flooplanning, but i have passed quiete often across this
> > keyword especially in vhdl references( as well as testbench );
> > unfortunately i have never understood it

It's also used in other related contexts. For example, a design with 
several identical subunits may have parts swapped round at PCB layout 
time. The changes are back-annotated to the schematic (or sometimes not 
:-((( )

--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 26638
Subject: Re: UCF Question
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Mon, 23 Oct 2000 09:24:11 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> Using a DLL will fix your timing problems. Opps, I see that you are
> using (or planning to use) a SpartanXL, no DLL. You can use the two sets
> of FFs as you mentioned, but you will need to specify only one of the
> offset constraints. They way they are used, you only need to specify the
> setup time, not the hold. So you should use the OFFSET IN BEFORE
> constraint and the tool should work properly on both clock edges.

Better yet: use an external PLL clock buffer device that's got 1X and 2X
outputs.  Drive the "External Logic" from the 1X clock and the FPGA from
the 2X clock.  Pay attention to board layout (make those clock lines,
including the feedback line, the same length) and you should be fine.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26639
Subject: Re: RS422 interfacing to a FPGA ?
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Mon, 23 Oct 2000 09:26:39 -0700
Links: << >>  << T >>  << A >>
Dan wrote:
> 
> Hello,
> 
> I need to interface a digital camera to a Xilinx FPGA.
>  (SMD-1M15  http://www.smd.com/products/1M15.asp)
> 
> The camera outputs its clock and pixel data as RS422. How do I convert this
> to something the FPGA can input ?

Use a standard differential-to-single-ended converter chip.  Lucent,
Motorola, TI, etc all make 'em.  They usually come four receivers to a
16-pin package.  I've been using the Lucent parts.  They work fine.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26640
Subject: Re: Typical toggle rates for power estimation ...
From: Ray Andraka <ray@andraka.com>
Date: Mon, 23 Oct 2000 17:37:38 GMT
Links: << >>  << T >>  << A >>
yes.  Extremely application dependent.  If it is a one channel streaming data in
parallel format, then you usually get alot of correlation between adjacent
samples, so there is not a whole lot of sample to sample activity in the upper
bits.  Interleave a second channel, and you get alot of avtivity if they are out
of phase wrt each other.  Activity in bit serial depends on the amplitude of the
signal.  If small compared to the bits available, then the data stays the same
for several bits in a row...no activity.  For a large signal, this is not as
likely.  You really have to know what the data is expected to do in your
application

Steven Derrien wrote:
> 
> Ray Andraka wrote:
> >
> > Actually, 50% is for practical purposes an upperbound if you assume random
> > states from cycle to cycle.  When you put real data through the system, this can
> > be reduced considerably,
> 
> To what kind of values ? 12 % 25 % ?
> 
> > as the real data tends to be correlated from sample to
> > sample.  The opposite might be true if you have two interleaved data streams
> > going through the same logic.
> 
> So, as far as i understand, this rate is VERY application dependent.
> 
> Thanks
> 
> Steven
> 
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26641
Subject: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
From: howard@recruitexpress.com (Recruit Express)
Date: Mon, 23 Oct 2000 17:50:38 GMT
Links: << >>  << T >>  << A >>
WIRLESS PDA  DEVELOPERS - San Jose
ASIC, FPGA, Windows Device Drivers 

Pre-IPO firm in San Jose area needs several developers for
new modules and components to be developed for use with
wireless PDA devices.  This is a new technology and a 'fresh
paint' - clean canvas' opportunity for you!

Hardware engineers should have 3 years design experience
in FPGA and ASIC.   

Software engineers should have 2 years development experience -  
on Windows device drivers and be proficient in C.   

We want to hire you immediately!  Our salary range is from
$80K to $125K plus other financial opportunities - based upon
the depth of your skills and the breadth of your experience.  

We are interested in persons living in the Bay Area only.  
We prefer to offer permanent employment but will consider
contractors.  U.S. citizenship or work permit required.  
We will sponsor visas of persons living in the Bay Area.


Recruit EXpress, our search firm, will pay you a $3,000.00
bonus if you are hired - or if the persons you refer to them 
are also hired for our openings. We have six openings.


Call or send your resume to Rex or Howard Frankel, at
Recruit EXpress
 (713) 666-1001 ....  or fax (713) 666-9993.  Their email is: 

REX@RecruitEXpress.com

or

HOWARD@RecruitEXpress.com

 


Article: 26642
Subject: Re: PCI Core : Clock Problem
From: "Walter Haas" <walter_haas@pmc-sierra.com>
Date: Mon, 23 Oct 2000 11:56:19 -0700
Links: << >>  << T >>  << A >>
Hello all,

Well, as I suspected, it didn't make a difference. The problem is the top level synthesis file...if you put a syn_maxfan attibute on the design (described as Max Fan Out in the Synplify Implementation Options), and you have more registers hanging off that black box pin than the fanout limit, buffers are inserted.

So...the long and short is that you *don't* have to synthesize the user module seperately if you don't want to, which to me, makes sense.

Article: 26643
Subject: Re: XILINX Download cable with USB
From: Juergen Otterbach <juergen.otterbach@t-online.de>
Date: Mon, 23 Oct 2000 21:08:44 +0200
Links: << >>  << T >>  << A >>
Dies ist eine mehrteilige Nachricht im MIME-Format.
--------------319F0DD20608577E43AFBE43
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dear FPGA user group, find attached a comment of Bill about USB driver for NT4.0. I
can not comment what is happening in the case of a XILINX Multilink cable...!?
Kind Regards  Juergen Otterbach


Betreff:             Re: USB Device Driver for NT4.0
Datum: Sun, 22 Oct 2000 16:05:49 -0700
Von:            wdk3@home.com (Bill)
An:            juergen.otterbach@t-online.de
Foren:        microsoft.public.windowsnt.apps

Juergen and other NT users:

I have found an outstanding program that enables USB mice, keyboards, printers
and cradles on NT 4.0.  I've purchased, downloaded and installed this $79
program and IT REALLY WORKS.  Go to www.bluewatersystems.com for more information
and ordering.

Bill


In article <39EDF110.F81D944D@t-online.de>, juergen.otterbach@t-online.de
says...
>
>Dies ist eine mehrteilige Nachricht im MIME-Format.

Ray Andraka schrieb:

> USB is not supported in NT.  If you find a way to do it, please share it as
> there are lots of us using NT.  For an NT box, you'll have to use either an old
> xchecker, a parallel III cable, or the Multilinx with the parallel port
> connection.
>
> Juergen Otterbach wrote:
> >
> > Dear XILINX users,
> > for my evaluation board I want to use the download cable with the USB
> > port on a PC Client with two USB ports. Therefore I want to enable the
> > USB interface in NT. Does anybody give me a hint were to find a USB
> > driver? Does anybody have experience? Or should I do not even think of
> > it?
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

--------------319F0DD20608577E43AFBE43
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Visitenkarte für Juergen Otterbach
Content-Disposition: attachment;
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begin:vcard 
n:;Juergen Otterbach
x-mozilla-html:FALSE
version:2.1
email;internet:juergen.otterbach@t-online.de
x-mozilla-cpt:;65535
fn:Juergen Otterbach
end:vcard

--------------319F0DD20608577E43AFBE43--


Article: 26644
Subject: Re: RS422 interfacing to a FPGA ?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 23 Oct 2000 12:50:11 -0700
Links: << >>  << T >>  << A >>
"Dan" <daniel.deconinck@sympatico.ca> writes:
> The camera outputs its clock and pixel data as RS422. How do I convert this
> to something the FPGA can input ?

quad RS-422 receiver chips:

National DS3486
AMD, TI Am26x32, Am26x33
TI SN75x153, SN75x175

Article: 26645
Subject: Re: xilinx floor planner issues
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Mon, 23 Oct 2000 19:55:15 GMT
Links: << >>  << T >>  << A >>
On Sun, 22 Oct 2000 12:02:35 GMT, erika_uk@my-deja.com wrote:

>Hi,
>
>could someone explain me what BACK ANNOTATION stands for ?
>
>not just in flooplanning, but i have passed quiete often across this
>keyword especially in vhdl references( as well as testbench );
>unfortunately i have never understood it

In timing analysis, back annotation is the process of inserting the
actual delays from the PAR onto your gate-level netlist. Synthesis
does an estimate of the routing delays and PAR gives you the most
accurate delays one can have without the actual silicon. PAR extracts
all the capacitive and routing loads and delays and you insert these
values on to your gate-level netlist which is the output of the
synthesis. 
This is useful for two reasons. One is that synthesis can do a better
job at resizing buffers with the actual delays instead of the
estimated delays. You can read in the delays into your (ASIC)
synthesis tool and do an inplace compile which doesn't change the
gates but resizes the drives of gates and buffers. This might give you
smaller area and lower power. You also need the actual delays to do
timing verification through either simulations of the annotated
gate-level or static timing analysis of the same.

Muzaffer

http://www.dspia.com

Article: 26646
Subject: Eric and Andy Thanks for help
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Mon, 23 Oct 2000 20:19:54 GMT
Links: << >>  << T >>  << A >>
Thanks for the info



Article: 26647
Subject: Re: Very Lucrative FPGA Jobs
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Mon, 23 Oct 2000 16:34:48 -0400
Links: << >>  << T >>  << A >>


Ron Huizen wrote:

> OK, this is just too hard to let pass by.  See comments inserted below:
>
> Edwin wrote:
>
> > Our client is looking for FPGA(Field Programmable Gate Array) designers to
> > work on a major effort to become the embedded technology supplier of choice
> > for the world's leading telecommunications and networking companies.
>
> Wow! That's quite a goal!  Can I buy some of their stock?
>
> > The
> > project is part of the effort to utilize FPGA designers
>
> Another lofty goal - utilizing FPGA designers :-)  This may be harder than the
> first one.
>
> > to help develop a
> > new line of CPU boards, communication interfaces such as T1/E1 spans or fast
> > serial ports) and protocol subsystems that can be sold off the shelf to
> > customers
>
> What a novel idea!  Boy, this sure is ground breaking stuff! Maybe these guys
> are going to
> invent COTS just like Mr. Gore invented the internet.
>
> > so that their internal engineers and designers can utilize these
> > platforms that will be used to develop chips
>
> Hang on, are these development tools or end products?
>
> > to be used in mobile phones and
> > telecommunications equipment.
>
> >
> >
> > Day-to-Day Responsibilities:
> >
> > Consultants or FPGA Designers (Field Programmable Gate Array) will be
> > involved with designing Programmable Logic Chips, otherwise known as PLD's.
>
> I wonder if he knows what PLD stands for?
>
> >
> > These PLD's make up a high density field of gates called FPGA Architectures.
>
> Hmm, better check with XILINX and Altera to see if they are aware of this.
>
> >
> > The FPGA designers will be involved with designing a "gate array" which is
> > an unfinished chip with electronic components that have not yet been
> > connected.
>
> Oh, maybe when they say FPGA designer, they mean actually designing the FPGA
> itself!
>
> > The designer will complete the chip by designing and adhering
> > the top metal layers which provide interconnecting pathways.
>
> What do they use for that?  An arc welder?  Super glue?
>
> > Once these
> > chips are designed, then they will be turned over to manufacturing for mass
> > production.
>
> If its so mass, wouldn't they be ASICs?
>
> > These chips will make up final products such as CPU boards,
> > communication interfaces, and protocol subsystems that will be used in the
> > telecommunications industry.
>
> So, the FPGA designer designs a chip which is mass produced and then used on
> your other
> boards??  Wonder what that "FP" stands for in FPGA??
>
> >
> > There are a total of 9 groups for that have anywhere from 4 to 14 FPGA
> > designers and Hardware Engineers that are working on the 3 major products
> > for different customers.  Submitted candidates will be placed in groups that
> > need the most help.
>
> That seems like a novel management approach.  Put people where they are needed
> the
> most.  I'd better write that one down so I don't forget it.
>
> > This is a cross functional project environment.
>
> Yeah, you're working with anywhere from 36 to 126 FPGA designers.  Sounds pretty
>
> cross functional to me.
>
> >
> > Candidates will always work under a principal engineer.
>
> Uh-oh. Sounds like trouble.
>
> > FPGA designers will
> > track their performance and product development with Microsoft Project that
> > will be reported to the head engineer.

We have head engineers where I work, only we call them plumbers or sometimes they
are architects.  75 years ago they must have been wizards because they put a moon on
the door to the head outback.

>
>
> What!  You want an FPGA designer to use Microsloth Project?  Oh well, at least
> they
> get to track their own performance.  Who's the head engineer?  Is he the guy who
>
> picks which programming head we get to use?
>
> >
> >
> > Essential Skills:
> >
> > Power PC
>
> Power PC? I never thought of that as a marketable skill, although I guess have
> years of
> experience plugging in my PC.
>
> > PCI Hardware and Software
>
> > VHDL
> > Embedded Hardware Design
> > 3 years experience in the industry
> >
> > Plus Skills:
> >
> > View Logic (Schematic Capture Product)
> > Simulation Experience (Signal Quality or Timing Simulation experience)
> > UNIX Experience
> > Telecom Experience (T1/E1 Interfaces)
>
> ----
> Ron Huizen
> BittWare


Article: 26648
Subject: Re: XILINX Download cable with USB
From: Ray Andraka <ray@andraka.com>
Date: Mon, 23 Oct 2000 20:51:17 GMT
Links: << >>  << T >>  << A >>
Unfortunately, I don't think this will help for the multilinx cable.  The fine
print says it won't work for digital cameras, usb scanners, or mice with extra
buttons.  Sounds like it is pretty much a driver to handle a few generic
devices.  If anyone learns anything different let us know.

Juergen Otterbach wrote:
> 
> Dear FPGA user group, find attached a comment of Bill about USB driver for NT4.0. I
> can not comment what is happening in the case of a XILINX Multilink cable...!?
> Kind Regards  Juergen Otterbach
> 
> Betreff:             Re: USB Device Driver for NT4.0
> Datum: Sun, 22 Oct 2000 16:05:49 -0700
> Von:            wdk3@home.com (Bill)
> An:            juergen.otterbach@t-online.de
> Foren:        microsoft.public.windowsnt.apps
> 
> Juergen and other NT users:
> 
> I have found an outstanding program that enables USB mice, keyboards, printers
> and cradles on NT 4.0.  I've purchased, downloaded and installed this $79
> program and IT REALLY WORKS.  Go to www.bluewatersystems.com for more information
> and ordering.
> 
> Bill
> 
> In article <39EDF110.F81D944D@t-online.de>, juergen.otterbach@t-online.de
> says...
> >
> >Dies ist eine mehrteilige Nachricht im MIME-Format.
> 
> Ray Andraka schrieb:
> 
> > USB is not supported in NT.  If you find a way to do it, please share it as
> > there are lots of us using NT.  For an NT box, you'll have to use either an old
> > xchecker, a parallel III cable, or the Multilinx with the parallel port
> > connection.
> >
> > Juergen Otterbach wrote:
> > >
> > > Dear XILINX users,
> > > for my evaluation board I want to use the download cable with the USB
> > > port on a PC Client with two USB ports. Therefore I want to enable the
> > > USB interface in NT. Does anybody give me a hint were to find a USB
> > > driver? Does anybody have experience? Or should I do not even think of
> > > it?
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26649
Subject: Re: RS422 interfacing to a FPGA ?
From: "Dan Kuechle" <dan_kuechle@i-tech.com>
Date: Mon, 23 Oct 2000 20:51:24 GMT
Links: << >>  << T >>  << A >>
So why can't you use a Virtex-E with the inputs set to LVD?  

Andy Peters <"apeters <"@> n o a o [.] e d u> wrote in article
<8t1ouc$bb5$2@noao.edu>...
> Dan wrote:
> > 
> > Hello,
> > 
> > I need to interface a digital camera to a Xilinx FPGA.
> >  (SMD-1M15  http://www.smd.com/products/1M15.asp)
> > 
> > The camera outputs its clock and pixel data as RS422. How do I convert
this
> > to something the FPGA can input ?
> 
> Use a standard differential-to-single-ended converter chip.  Lucent,
> Motorola, TI, etc all make 'em.  They usually come four receivers to a
> 16-pin package.  I've been using the Lucent parts.  They work fine.
> 
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
> 



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