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Messages from 26650

Article: 26650
Subject: Re: Very Lucrative FPGA Jobs
From: "Austin Franklin" <austin@dark88room.com>
Date: 23 Oct 2000 21:04:50 GMT
Links: << >>  << T >>  << A >>
> > 3 years experience in the industry

This is actually the one that gets me...a whole three years experience, and
they expect them to be able to do all this other stuff...I'd be impressed
if the guy knew what FPGA stood for with 3 years experience (in the
industry, of course ;-)

Their expectations are, to say the least, bizarre...at least in my book.


Article: 26651
Subject: [2]How safe is the algorithm implemented with FPGA?
From: Yu Chen <yuchen@edson.ee.ualberta.ca>
Date: 23 Oct 2000 22:16:12 GMT
Links: << >>  << T >>  << A >>
Hi guys,

Thanks a lot for all your inputs. I've learned a lot from them. 
And I really appreciate your advice. 

After finish reading all of these messages, I think I have to 
compromise somehow. I can bear with someone who just wants to 
copy the chip. But I still want to stop those who wants to figure 
out the algorithm. Is there any better way to achieve this goal?

Regards.
Yu Chen
 

Article: 26652
Subject: Specifying pin in design file
From: sac62513@saclink3.csus.edu (Don Teeter)
Date: 23 Oct 2000 22:19:32 GMT
Links: << >>  << T >>  << A >>
Maybe I'm not up to speed yet in finding answers in help files.  Though 
I've yet to see a help file that rewards time spent learning to navigate it.

I want to specify specific I/O pins in an XC4000E series part for certain 
parts of the design.  This should be easy and straightforward.  Can 
anyone take a moment to tell me what an hour of scouring books and help 
files could not?

S/W used = Foundation 2.1i

Thank you in advance.

d.r.t.


Article: 26653
Subject: Re: How safe is the algorithm implemented with FPGA?
From: Yu Chen <yuchen@edson.ee.ualberta.ca>
Date: 23 Oct 2000 22:29:48 GMT
Links: << >>  << T >>  << A >>
Hi guys,

Thanks a lot for all your inputs. I've learned a lot from them.
And I really appreciate your advice.

After finish reading all of these messages, I think I have to
compromise somehow. I can bear with someone who just wants to
copy the chip. But I still want to stop those who wants to figure
out the algorithm. Is there any better way to achieve this goal?

Regards.
Yu Chen

Article: 26654
Subject: Re: Atmel FPGA tools (was Re: Cheapy FPGA sw)
From: "eng" <int@net.net.net>
Date: Tue, 24 Oct 2000 10:07:37 +1000
Links: << >>  << T >>  << A >>

> You can test the toolset by buying the new FPSLIC demoboard.
> Will only set you back half a k$ and has a time limited license. (4 months
I
> believe)
> You can then subscribe for about $1k/year OR you can write FPSLIC
> application notes. Any such appnote approved by Atmel will delay
expiration
> by 6 months....

<ROLF>  Now there's an incentive to properly document some code for a change
;-)

Well done Atmel!

>
> --
> Best regards,
> ulf at atmel dot com
> The contents of this message is intended to be my private opinion and
> may or may not be shared by my employer Atmel Sweden
>
> "Russ.Shaw" <russell@webaxs.net> wrote in message
> news:39F19F96.1AB2E11C@webaxs.net...
>
>

Greg



Article: 26655
Subject: Re: Specifying pin in design file
From: "Kang Liat Chuan" <kanglc@agilis.st.com.sg>
Date: Tue, 24 Oct 2000 10:37:19 +0800
Links: << >>  << T >>  << A >>
Hi,

I used F2.1i too. Initially I tried to specify LOC property inside the pad,
but it doesn't support buses! Now I am using the UCF file. But you have to
implement the design once before you can put those "#NET io_net_name  LOC =
P111;" in the UCF file. When I use Mentor Graphics Design Architect, I can
specify everything (LOC, TNM, etc.) in the schematics before I do the
compilation. Is it possible to do like that in F2.1i?

Regards,
LC

Don Teeter <sac62513@saclink3.csus.edu> wrote in message
news:8t2dhk$r7e@news.csus.edu...
> Maybe I'm not up to speed yet in finding answers in help files.  Though
> I've yet to see a help file that rewards time spent learning to navigate
it.
>
> I want to specify specific I/O pins in an XC4000E series part for certain
> parts of the design.  This should be easy and straightforward.  Can
> anyone take a moment to tell me what an hour of scouring books and help
> files could not?
>
> S/W used = Foundation 2.1i
>
> Thank you in advance.
>
> d.r.t.
>



Article: 26656
Subject: Re: How safe is the algorithm implemented with FPGA?
From: Philip Freidin <philip@fliptronics.com>
Date: Mon, 23 Oct 2000 20:36:17 -0700
Links: << >>  << T >>  << A >>
On 23 Oct 2000 22:29:48 GMT, Yu Chen <yuchen@edson.ee.ualberta.ca> wrote:
>Hi guys,
>After finish reading all of these messages, I think I have to
>compromise somehow.

Right. No security system is perfect. The only issue is the $ barrier

>I can bear with someone who just wants to
>copy the chip. But I still want to stop those who wants to figure
>out the algorithm.

Right. Copy as in "photocopy" and copy as in reverse engineer
the function and use the info in a new design. 

>Is there any better way to achieve this goal?
>Regards.
>Yu Chen

Since what you want to do is protect the algorithm, then what you
must be worried about is reverse engineering of the configuration
data.

Regardless of all the discussion in this news group, there has
NEVER been a cited case of a bitstream being reverse engineered
to reveal a design.

The only known instance of a bitstream format being reverse
engineered (this is less difficult than reverse engineering a design) is
when Neocad reverse engineered the Xilinx bitstream format, and it
reportedly represented multiple man-years effort, and that was for
the fairly simple XC3000 family.

If someone really wants to reverse engineer a design in an FPGA,
they are going to require less effort by just hooking a logic
analyzer to all the pins, and watch it operate as long as necessary
to figure out what is going on, and then design from scratch an
equivalent design. This will be easier than extracting a design
from the bitstream. But it will still be very hard for large and complex
designs. (may take months/years of work. Given product life cycles
of designs these days, the investment in reverse engineering an
existing design is usually better spent on just creating a new design.)






========================
Philip Freidin
Mindspring that acquired Earthlink that acquired Netcom has
decided to kill off all Netcom Shell accounts, including mine.
My new primary email address is    philip@fliptronics.com
Please update your address book, sorry for the inconvenience

Article: 26657
Subject: Re: UCF Question
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 23 Oct 2000 23:43:15 -0400
Links: << >>  << T >>  << A >>
I am missing something here. If you delay the clk by 9 nS and the data
by 16 nS, with a 6 nS setup time, you will *miss* the timing window by 1
nS. So the tool is correct, no?


yuryws@my-deja.com wrote:
> 
> The problem with using only OFFSET IN BEFORE is that my data is valid
> for a fraction of clock period only around each clock edge, so for
> example say OFFSET IN BEFORE = 6 ns, the tools will find that the
> following two results are accepatable:
> 
> For the sake of discussion let the clock period be 60 ns.
> 
>    1) CLK delayed by 9 ns, Data delayed by 16 ns (the tool will report 1
> ns slack (16-(9+6)), which is OK)
>    2) CLK delayed by 2 ns, Data delayed by 16 ns (the tool will report 8
> ns slack (16-(2+6)), which is not OK, since my data is invalid in this
> region (data is only valid for 6 ns before and after each edge).
> 
> In addition the tools may have a difficult time meeting the constraints
> specified, because the tools does not take advatage of the fact that the
> clock edge could be ahead of data by as much as 6 ns.
> 
> -- Yury

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26658
Subject: Re: How secure from pirates is a Quick Logic part ?
From: David Forbes <dforbes@azspamnet.com>
Date: Mon, 23 Oct 2000 21:15:10 -0700
Links: << >>  << T >>  << A >>
"Dan" <daniel.deconinck@sympatico.ca> wrote:

> Hello,
> 
> What level of effort is required to copy a Quick Logic part ?
> 
> Dan
> 
> 

Dan,

There's an article in this month's EDN about this issue. They point out 
how pirate-proof the QuickLogic parts are. The Quicklogic data books 
also describe this feature - the reason is that the antifuse is actually 
a sub-micron melted spot right underneath the metalization, so it would 
be very hard even to dismantle the chip and read it visually, and the 
fuses become inaccessible elecrically after the device is programmed. 

You do have to get QuickLogic to program the parts for you at their 
regional office, since the programming process is apparently rather 
obscure and time-consuming. 

So other than exposing your programming file to others while it's being 
transported to the company for programming, it looks like a pretty safe 
technology to hide your IP in.

--David Forbes
Tucson AZ

Change spamnet to starnet before replying.

Article: 26659
Subject: New PACT 50 GOP Reconfigurable Processor
From: "EMF" <emf83@hotmail.com>
Date: Tue, 24 Oct 2000 04:16:00 GMT
Links: << >>  << T >>  << A >>
The new 50 GOPs processor from PACT looks like an interesting alternative to
FPGAs for high speed DSP.  I need something that has high I/O and memory
bandwidth and a lot of processing power and their spec’s look outstanding.

51.2 GigaOps (32-bit)
12.8 GigaMACs (32-bit)
3.2 Gigabyte/s external memory bandwidth
12.8 Gigabyte/s internal memory bandwidth
6.4 Gigabyte/s sustained I/O bandwidth
0.4 Terabyte/s internal data bandwidth

Has anyone else looked at this technology?  It just appeared in the press a
few weeks ago.

Their web site is www.pactcorp.com




Article: 26660
Subject: Re: RS422 interfacing to a FPGA ?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 23 Oct 2000 23:39:37 -0700
Links: << >>  << T >>  << A >>
Andy Peters <"apeters <"@> n o a o [.] e d u> wrote in article
> The camera outputs its clock and pixel data as RS422. How do I convert
> this to something the FPGA can input ?

"Dan Kuechle" <dan_kuechle@i-tech.com> writes:
> So why can't you use a Virtex-E with the inputs set to LVD?  

I don't know the Virtex-E specs, but in general LVD doesn't have the
common-mode voltage range needed for RS-422.  Remember what the "L"
stands for.


Article: 26661
Subject: Re: New PACT 50 GOP Reconfigurable Processor
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 23 Oct 2000 23:42:20 -0700
Links: << >>  << T >>  << A >>
"EMF" <emf83@hotmail.com> writes:
> The new 50 GOPs processor from PACT looks like an interesting alternative to
> FPGAs for high speed DSP.  I need something that has high I/O and memory
> bandwidth and a lot of processing power and their specs look outstanding.
> 
> 51.2 GigaOps (32-bit)
> 12.8 GigaMACs (32-bit)

What's an "Op"?  It looks like either multiply and add each take two "Ops",
or multiply takes three "Ops" and add takes one?

Article: 26662
Subject: How to reduce Tco?
From: "Frank Z.F Xie" <frank.xie@latticesemi.com>
Date: Tue, 24 Oct 2000 14:46:06 +0800
Links: << >>  << T >>  << A >>
Hi, there

Currently I was running some test case with Xilinx VirtexE device. But I
found the Tco time of it is quite long, for a simple DFF, the Tco is around
6ns for device XCV100E-8CS144. I used constraint editor to control time, but
no good result. I'm not quite familiar with floorplanner. Does anyone know
how to reduce it, to around 4ns.

Thanks

--

Zhengfan Xie
frank_xie@writeme.com



Article: 26663
Subject: Re: How safe is the algorithm implemented with FPGA?
From: nweaver@soda.CSUA.Berkeley.EDU (Nicholas Weaver)
Date: 24 Oct 2000 06:49:35 GMT
Links: << >>  << T >>  << A >>
In article <ktv9vs46blbr2jec18fsm1pkot6lh8kp6k@4ax.com>,
Philip Freidin  <philip@fliptronics.com> wrote:
>>Is there any better way to achieve this goal?
>>Regards.
>>Yu Chen
>
>Since what you want to do is protect the algorithm, then what you
>must be worried about is reverse engineering of the configuration
>data.
>
>Regardless of all the discussion in this news group, there has
>NEVER been a cited case of a bitstream being reverse engineered
>to reveal a design.

	Probably only because of economic interest.

	And, with a tool like Jbits for the Virtex, it is pretty
reasonable to go from a bitfile to a technology mapped (lut mapped)
netlist.  

	The result can be pretty hard to understand, with obsfucation
and other confusion, but going from bitfile->lut mapped netlist is a
reasonable operation.  If there is a SIGNIFICANT ecomonic interest for
someone to do so, he or she will.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 26664
Subject: Re: New PACT 50 GOP Reconfigurable Processor
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 24 Oct 2000 00:04:48 -0700
Links: << >>  << T >>  << A >>
Is this spam or what???

emf83@hotmail.com has never posted to this group (and according to
deja.com, no other groups either, ever). Today s/he has posted the
same message to 7 groups including ours.

Anyone want to take bets on emf83's current employer?

On Tue, 24 Oct 2000 04:16:00 GMT, "EMF" <emf83@hotmail.com> wrote:
>The new 50 GOPs processor from PACT looks like an interesting alternative to
>   blah blah blah
>Has anyone else looked at this technology?  It just appeared in the press a
>few weeks ago.

Philip Freidin
Fliptronics

Article: 26665
Subject: Xilinx configuration: JTAG and SPROM
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Tue, 24 Oct 2000 11:15:31 +0200
Links: << >>  << T >>  << A >>
Hello all
I wonder if it's possible to configure an FPGA through the JTAG
interface when a PROM is connected to the device.
Won't this generate a conflict?
-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
Fax +33 1 46 67 51 01      http://www.IPricot.com/

Article: 26666
Subject: Re: RS422 interfacing to a FPGA ?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 24 Oct 2000 22:38:22 +1300
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> 
> Andy Peters <"apeters <"@> n o a o [.] e d u> wrote in article
> > The camera outputs its clock and pixel data as RS422. How do I convert
> > this to something the FPGA can input ?
> 
> "Dan Kuechle" <dan_kuechle@i-tech.com> writes:
> > So why can't you use a Virtex-E with the inputs set to LVD?
> 
> I don't know the Virtex-E specs, but in general LVD doesn't have the
> common-mode voltage range needed for RS-422.  Remember what the "L"
> stands for.

 LVD itself does not have the -7V/+12V common mode range of RS422, but
if you look at a RS422 receiver, they way they deliver the wide CMVR,
is to use dropper resistors.
 So, if you take the 100mV span on LVD, and a nom 1,5V bias point,
then use a 7:1 divider, you get -9V .. +13.5V common mode range,

 ie, you can trade off sensitivity for common mode range.

 If the camera is local, and unlikely to be unplugged, the FPGA+Divider
solution is practical.
 If it is remote, and often de-connected then ESD protection is an
important
issue, and the separate buffers can win 

-jg

-- 
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 26667
Subject: Re: Xilinx configuration: JTAG and SPROM
From: Etienne Racine <etienne@cae.ca>
Date: Tue, 24 Oct 2000 06:45:08 -0400
Links: << >>  << T >>  << A >>
Bonjour Nicolas,

Nicolas Matringe wrote:

> I wonder if it's possible to configure an FPGA through the JTAG
> interface when a PROM is connected to the device.

> Won't this generate a conflict?

Non. Programming an FPGA via JTAG is done only by performing JTAG
operations on the FPGA itself. It's just like using another input for
configuration. Any other JTAG device within the chain will be placed in
BYPASS (including any JTAG-capable configuration PROM like the XC18vXX).

There might be some tweaking required to configure properly a device,
but generally it's only required when you want to use the JTAG clock
(TCK) as a starting clock. You may want to check app note XAPP017 for
XC4K devices and XAPP138 for the Virtex family.

Bonne journée,

Étienne.
--
      ______ ______
*****/ ____// _  \_\*************************************************
*   / /_/_ / /_/ / /       Etienne Racine, Hardware Designer        *
*  / ____// __  /_/           Visual Systems Engineering            *
* / /_/_ / / /\ \ \              CAE Electronics Ltd.               *
*/_____//_/_/**\_\_\*************************************************



Article: 26668
Subject: Virtex Dual Port RAM simulation failure in Modelsim
From: Steven Sanders <sanders@imec.be>
Date: Tue, 24 Oct 2000 12:22:37 +0100
Links: << >>  << T >>  << A >>
Hello,

I`ve instantiated some Dual Port Ram in an entity like this:

component RAMB4_S8_S8
    port (wea, web, ena, enb, rsta, rstb, clka, clkb : in  std_logic;
           addra, addrb                              : in 
std_logic_vector(8 downto 0);
           dia, dib                                  : in 
std_logic_vector(7 downto 0);
           doa, dob                                  : out
std_logic_vector(7 downto 0));
  end component;

I apply all correct signals to write some addresses in PORTA and read
the
same addresses in PORTB, but when I functionally simulate my design in
Modelsim, I only
get zero-output at PORTB. I get no errors and I`ve loaded the simprim
and unisim libs...

Any hints?

Thanx in advance.

Steven.

Article: 26669
Subject: timing simulation with Xilinx and Fusion/SpeedWave
From: Franz Hollerer <hollerer@hephy.oeaw.ac.at>
Date: Tue, 24 Oct 2000 14:05:07 +0200
Links: << >>  << T >>  << A >>
Hi,

I have some questions about timing simulation and I hope
that somebody can help me.

The Xilinx software creates time_sim.vhd and time_sim.sdf.
I now want to do a timing simulation with Fusion/SpeedWave.
It principally works. But if I choose time_sim.sdf for further
timing data, fusion prints a lot of error messages (see below).

Do I really  need the .sdf file for a correct timing simulation or is
the
time_sim.vhd file enough?

Any hints?

Thanks
Franz Hollerer

-----------------------------------------------------------------------
error message
-----------------------------------------------------------------------
Starting VITAL SDF Backannotation.
  Processing SDF file: D:\hollerer\vhdl\tcs\export_dir\time_sim.sdf
    Hierarchical Path Prefix:    /
    Timing mode:                 Max
    Hierarchy divider character: /
    Timescale factor:            0.001 ns
** Error at SDF file line number 21:
For this hierarchical path name in the SDF file:
  '/PRE1_CNT_REG_0_Q'
Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design.
** Error at SDF file line number 22:
For this hierarchical path name in the SDF file:
  '/PRE1_CNT_REG_0_Q'
Could not find region level 'PRE1_CNT_REG_0_Q' in the VHDL design.
** Error at SDF file line number 23:
For this hierarchical path name in the SDF file:
  '/PRE1_CNT_REG_0_Q'
:
:
:
and so on

--
Institut fuer Hochenergiephysik
Nikolsdorfer Gasse 18
1050  Wien
Austria

Tel: (+43-1)5447328/50



Article: 26670
Subject: Re: New PACT 50 GOP Reconfigurable Processor
From: steve (Steve Rencontre)
Date: Tue, 24 Oct 2000 13:13 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <428J5.13821$1S5.1327906@newsread1.prod.itd.earthlink.net>, 
emf83@hotmail.com (EMF) wrote:

> [snipped]

Spam. At least it's more-or-less targetted for once.

Why can't manufacturers just be honest about plugging a product? Nobody's 
fooled. If I need the sort of thing they're selling, I'm automatically 
going to prefer a competitor now.

--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 26671
Subject: IOBUF's replaced by IBUF's
From: Markus Michel <mmichel@kontronmedical.ch>
Date: Tue, 24 Oct 2000 14:37:50 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------AC759177DA537651F08C081D
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello all,
I have a strange problem with Xilinx Alliance 2.1i SP6:

bidirectional data pins are implemented in VHDL; the synthesis tool
correctly places IOBUF's. Functional simulation is o.k.
But MAP removes all output signals including the tristate
control signal, and replaces all IOBUF's by IBUF's.

What could be the problem?

Remark:
When I myself replace the IOBUF's by OBUF's, the output direction
works correctly; the mapper does not touch them.

Thanks for your help.
M. Michel

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title:dipl. El'Ing. ETH
adr;quoted-printable:;;Reinacherstr. 131=0D=0AP.O. Box;CH- 4002 Basel;;;Switzerland
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--------------AC759177DA537651F08C081D--


Article: 26672
Subject: Re: How safe is the algorithm implemented with FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 24 Oct 2000 13:23:51 GMT
Links: << >>  << T >>  << A >>
True enough, but that is only the first step (and arguably the easiest step) of
reverse engineering a design from the bitstream.  Once the design is
reconstituted as a netlist of LUTs, you have essentially a flat representation
of the design with LUTs, FF's and carry chain elements as its only primitives. 
WHile this can be reverse engineered, the effort to do so is substantial even
for small devices (I know, I had to  discover the function of a 2064 a few years
ago for a client...that one only has 64 very simple logic cells and it was no
small effort)  The effort to do the discovery was at least 3x the effort for a
design from scratch.  I suspect that effort goes up faster than linear as the
number and complexity of the LUTs is increased.

So the bottom line is the tools out there now make it possible to recover the
flat primitive level design, which is essentially what you get if you capture
the backannotated netlist from the tools (uses simprim library).  Getting that
netlist into a form that allows you to understand the design is another matter
altogether.  To get an idea of the effort it would take, take a *.vho output
from the placer on one of your designs and try to figure out from there how it
works.  It's not trivial even when you know the design!  

Nicholas Weaver wrote:
> 
> In article <ktv9vs46blbr2jec18fsm1pkot6lh8kp6k@4ax.com>,
> Philip Freidin  <philip@fliptronics.com> wrote:
> >>Is there any better way to achieve this goal?
> >>Regards.
> >>Yu Chen
> >
> >Since what you want to do is protect the algorithm, then what you
> >must be worried about is reverse engineering of the configuration
> >data.
> >
> >Regardless of all the discussion in this news group, there has
> >NEVER been a cited case of a bitstream being reverse engineered
> >to reveal a design.
> 
>         Probably only because of economic interest.
> 
>         And, with a tool like Jbits for the Virtex, it is pretty
> reasonable to go from a bitfile to a technology mapped (lut mapped)
> netlist.
> 
>         The result can be pretty hard to understand, with obsfucation
> and other confusion, but going from bitfile->lut mapped netlist is a
> reasonable operation.  If there is a SIGNIFICANT ecomonic interest for
> someone to do so, he or she will.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26673
Subject: Re: New PACT 50 GOP Reconfigurable Processor
From: Ray Andraka <ray@andraka.com>
Date: Tue, 24 Oct 2000 13:30:41 GMT
Links: << >>  << T >>  << A >>


EMF wrote:
> 
> The new 50 GOPs processor from PACT looks like an interesting alternative to
> FPGAs for high speed DSP.  I need something that has high I/O and memory
> bandwidth and a lot of processing power and their spec’s look outstanding.
> 
> 51.2 GigaOps (32-bit)
> 12.8 GigaMACs (32-bit)

^^^^ so where's the big advantage?  YOu can do this on an FPGA using a fraction
of the power (see my article in the August 7, 2000 EETimes, available through my
website) .  I've got a paper on my website documenting a virtex 1000 design that
does 11 GigaMACs in about 55% of the chip.  THe accumulator in this case is >40
bits, which means there is no rounding errors in long sums of products like you
would get with a fixed 32 bit data path.

> 3.2 Gigabyte/s external memory bandwidth
> 12.8 Gigabyte/s internal memory bandwidth
> 6.4 Gigabyte/s sustained I/O bandwidth
> 0.4 Terabyte/s internal data bandwidth
> 
> Has anyone else looked at this technology?  It just appeared in the press a
> few weeks ago.
> 
> Their web site is www.pactcorp.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26674
Subject: Re: Virtex Dual Port RAM simulation failure in Modelsim
From: Ray Andraka <ray@andraka.com>
Date: Tue, 24 Oct 2000 13:38:04 GMT
Links: << >>  << T >>  << A >>
to get the data out B you need the write to A to be successful as well as the
read from B.  Check that the RST inputs are '0' on both sides, that you have
valid clocks both sides, that the ENA pins are '1' both sides, and that the WE
is appropriately operated.  Also, you can't read from the same address you are
writing to on any given cycle.

Steven Sanders wrote:
> 
> Hello,
> 
> I`ve instantiated some Dual Port Ram in an entity like this:
> 
> component RAMB4_S8_S8
>     port (wea, web, ena, enb, rsta, rstb, clka, clkb : in  std_logic;
>            addra, addrb                              : in
> std_logic_vector(8 downto 0);
>            dia, dib                                  : in
> std_logic_vector(7 downto 0);
>            doa, dob                                  : out
> std_logic_vector(7 downto 0));
>   end component;
> 
> I apply all correct signals to write some addresses in PORTA and read
> the
> same addresses in PORTB, but when I functionally simulate my design in
> Modelsim, I only
> get zero-output at PORTB. I get no errors and I`ve loaded the simprim
> and unisim libs...
> 
> Any hints?
> 
> Thanx in advance.
> 
> Steven.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com



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