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Messages from 26525

Article: 26525
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Ray Andraka <ray@andraka.com>
Date: Thu, 19 Oct 2000 07:53:55 GMT
Links: << >>  << T >>  << A >>


Phil Hays wrote:
> 
> Ray Andraka wrote:
> 
> > The area constraints in 3.1 do work reasonably well with a hierarchical design.
> > As for the naming of stuff, the part that does not keep the same name from run
> > to run on the synthesizer is the inferred combinatorial logic.  Flip-flops tend
> > to keep the names (I label everything) if you label your processes.  If you
> > follow good high speed FPGA design so that your logic is mostly 1 level, then
> > you can get away with floorplanning the flip-flops and leaving the luts off.
> 
> There are differences in the types of designs we do.  I have found that I both
> need to put multiple levels of logic between flip-flops, and that at the speeds
> I've done designs (up to 133 MHz), that I can put multiple levels of logic
> between flip-flops with correct placement.  When using multiple levels of logic,
> I have in the past hand mapped logic into entities and decorate these with the
> correct magic to produce FMAPs.  These FMAPs have stable names, and can be
> floorplanned.  Amplify gets almost as good of results, and is much easier and
> faster.  Other than getting $$ from management.
> 
> > Hierarchy is the
> > biggest help for reuse, rapid design and floorplanning.  The big designs tend to
> > be made up of the same smaller pieces as the small designs, so it is very rare
> > that I have to start a floorplan from scratch.
> 
> One thing I'd like to see in Amplify is hierarchical design.  It would be nice
> on some designs to be able to floorplan an entity, and then step multiple copies
> of that entity across a FPGA.  Or to floorplan an entity and move that to a
> different design.
> 
> > One last thing, I run into people from time to time that tell me that you can't
> > do million + gate designs this way (using Rlocs and fmaps).  The proof is in the
> > pudding, though.  It is a quite successful flow for me.  I figure I've done well
> > over 10 million Virtex gates in the last 8 months, the majority of those are
> > being clocked over 100 MHz and every one of them is in a -4 (slow) part.  Yes,
> > all of those designs have been floorplanned, and all but one have RLOCs and
> > FMAPs embedded in the code.
> 
> I am impressed.  However, not all design gates are the same.  Some fairly large
> designs are completely definable on a single page, and some smaller designs need
> hundreds of pages to define them.  I seem to get the second type.

An XCV400-4 design I delivered yesterday has 173 pages of VHDL in 8 point type
spread across 39 files.  I find that is rather typical.  THe key point is that
reuse is where I get the productivity from, and without the RLOCs in the code I
have to floorplan everything every time.  With the RLOCs in the code, along with
parameterization, I get the benefit of my past work without having to floorplan
it again. You can't do that with Amplify, as it doesn't do hierarchical
floorplanning.  As I've said before, it might be a handy tool for my occasional
use, but its marginal utility to me is not worth the hefty premium.

> 
> For your design style, I don't think that Amplify would help you much.  For me,
> it does.
> 
> --
> Phil Hays

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26526
Subject: Re: Synopsys FPGA Compiler II on Solaris
From: =?iso-8859-1?Q?J=F6rg?= Ritter <ritter@informatik.uni-halle.de>
Date: Thu, 19 Oct 2000 14:50:32 +0200
Links: << >>  << T >>  << A >>
Hi,

> > I'm using the fc2 under solaris2.6 and 2.7 (SunOS 5.6 and 5.7).
> > Do you get window decorations when using KDE as the window manager ?
>
> No, the window frames don't appear on the screen. I have to start
> FC2 under CDE to resize the windows. Seems a common problem for some
> tools, the previous Primetime showed the same behavior, with the newest=

> version it's gone.
> Do you have any bugfix for that?

using fvwm was the only solution for me.

ciao
J=F6rg



Article: 26527
Subject: Re: Synopsys FPGA Compiler II on Solaris
From: acher@in.tum.de (Georg Acher)
Date: 19 Oct 2000 13:57:47 GMT
Links: << >>  << T >>  << A >>
In article <39EEEE18.ECBD5165@informatik.uni-halle.de>,
 =?iso-8859-1?Q?J=F6rg?= Ritter <ritter@informatik.uni-halle.de> writes:
|> Hi,
|> 
|> > > I'm using the fc2 under solaris2.6 and 2.7 (SunOS 5.6 and 5.7).
|> > > Do you get window decorations when using KDE as the window manager ?
|> >
|> > No, the window frames don't appear on the screen. I have to start
|> > FC2 under CDE to resize the windows. Seems a common problem for some
|> > tools, the previous Primetime showed the same behavior, with the newest=
|> 
|> > version it's gone.
|> > Do you have any bugfix for that?
|> 
|> using fvwm was the only solution for me.

A bit OT, but it may help:
I haven't actually tried it with this particular Synopsys version, but KDE can move
windows with <ALT>+<Button1> and resize them with <ALT>+<Button3>, this can be adjusted 
in the KDE Control Center under Windows/Mouse. A window frame is not necessary, it works
even with the shaped windows of xeyes.
-- 
         Georg Acher, acher@in.tum.de         
         http://www.in.tum.de/~acher/
          "Oh no, not again !" The bowl of petunias          

Article: 26528
Subject: UCF question
From: yuryws@my-deja.com
Date: Thu, 19 Oct 2000 14:08:21 GMT
Links: << >>  << T >>  << A >>
Need to create UCF constraints to cover the following scenario:

1. 16 bits are being clocked on the falling edge of CLK.
2. 16 bits are being clocked on the rising edge of CLK.
3. Data is valid 6 ns before and 6 ns after every CLK edge.
4. Shortest time between CLK edges is 25 ns.
5. Data and the clock come into Xilinx (Spartan XL) through input pads.
6. CLK is fed through a non-clock pad.
                                        ________
              |\ IBUF      |\BUFGLS     |  FF  |
              | \          | \          |      |
     PAD______|  \_________|  \_________|C     |
        CLK   |  /         |  /         |      |
              | /          | /          |      |
              |/           |/           |      |
                                        |      |
                                        |      |
              |\ IBUF                   |      |
              | \                       |      |
     PAD______|  \______________________|D    Q|____DATA_Q(i)
      DATA(i) |  /                      |      |
              | /                       |      |
              |/                        |______|

                __________            __________            ________
DATA(i) -------|__________|----------|__________|----------|________
        _____________                       _____________________
CLK                  |_____________________|                     |

                  6ns 6ns              6ns  6ns
               |<----/--->|          |<----/--->|

                              25 ns                  25 ns
                     |<------------------->|<------------------->|



Thanks,
        Yury Wolf /  Realtime Data


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Article: 26529
Subject: FPGA DESIGNER LONG ISLAND
From: "Vincent Jachetta - Multidyne" <vincent@multidyne.com>
Date: Thu, 19 Oct 2000 14:14:03 GMT
Links: << >>  << T >>  << A >>
Looking for Xilinx FPGA designer on Long Island. Slary open, benefits.
Call (516)671-7278 ext 103
www.multidyne.com



Article: 26530
Subject: UCF Question
From: yuryws@my-deja.com
Date: Thu, 19 Oct 2000 14:15:57 GMT
Links: << >>  << T >>  << A >>
Need to create UCF constraints to cover the following scenario:

1. 16 bits are being clocked on the falling edge of CLK.
2. 16 bits are being clocked on the rising edge of CLK.
3. Data is valid 6 ns before and 6 ns after every CLK edge.
4. Shortest time between CLK edges is 25 ns.
5. Data and the clock come into Xilinx (Spartan XL) through input pads.
6. CLK is fed through a non-clock pad.



So, the circuit is:

CLK @ non-clock pad---IBUF---BUFGLS--->FF
Data @ pad------------IBUF-------------FF

(Tried to post the circuit using ASCII, bit it comes out completely
distorted)

Thanks,
        Yury Wolf /  Realtime Data


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Article: 26531
Subject: UCF Question
From: yuryws@my-deja.com
Date: Thu, 19 Oct 2000 14:17:48 GMT
Links: << >>  << T >>  << A >>
Need to create UCF constraints to cover the following scenario:

1. 16 bits are being clocked on the falling edge of CLK.
2. 16 bits are being clocked on the rising edge of CLK.
3. Data is valid 6 ns before and 6 ns after every CLK edge.
4. Shortest time between CLK edges is 25 ns.
5. Data and the clock come into Xilinx (Spartan XL) through input pads.
6. CLK is fed through a non-clock pad.



So, the circuit is:

CLK @ non-clock pad---IBUF---BUFGLS--->FF
Data @ pad------------IBUF-------------FF

(Tried to post the circuit using ASCII, bit it comes out completely
distorted)

Thanks,
        Yury Wolf /  Realtime Data


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Before you buy.

Article: 26532
Subject: How safe is the algorithm implemented with FPGA?
From: Yu Chen <yuchen@edson.ee.ualberta.ca>
Date: 19 Oct 2000 16:54:08 GMT
Links: << >>  << T >>  << A >>

Hi, there,

I'd like to know more about this topic:
How safe is the algorithm which is implemented using Altera's products? I mean, in case someone less got the FPGA(or ASIC)with the algorithm coded in it and he wanted to steal the algorithm, how much effort is needed for him to get the algorithm or just duplicate another FPGA( or ASIC) with the same function? We are thinking about using Altera's product to protect our own algoithms from being stolen. Please also let me know where I could get more information about this.

Thank you in advance.
Yu Chen


Article: 26533
Subject: Re: scripting with xilinx tools (foundation) ????
From: erika_uk@my-deja.com
Date: Thu, 19 Oct 2000 17:40:16 GMT
Links: << >>  << T >>  << A >>
why is the the benefit from using  Script command file
In article <39EE31D1.16735214@xilinx.com>,
  brian.philofsky@xilinx.com wrote:
> This is a multi-part message in MIME format.
> --------------30802F542B8914A23CAC4176
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> Hello Peter,
>
>      There is a command-line command called xflow which will take an
EDIF file
> and run it through the the Xilinx tools including bitstream creation
and
> simulation file creation.  Xflow is availible in Foundation, Alliance
and ISE
> packages.  You can run this command from a TCL script in Synplfy (or
FPGA
> Express or Leonardo or Modelsim or any TCL interface) if you wish
using the
> "exec" command, you can run it from a batch/shell script, or just type
it on the
> command-line.  You can run it with all default settings or customize
the varoius
> switches and design flow.  It is pretty simple to use and learn.  I
find this
> much easier to use than the TCL interface with Quartus and I am sure
you will as
> well once you get to know it a bit.
>
>     Complete documentation on xflow can be found at:
>
http://toolbox.xilinx.com/docsan/3_1i/data/common/dev/chap22/dev22000.ht
m
>
>    Hope this works for you.
>
> --  Brian
>
> peter wrote:
>
> > Hi,
> >
> > As an asic designer, I used altera components for prototyping
(realtime
> > functional verification of subblocks) in the past.  Currently (new
job), we
> > are using the Xilinx environment.
> > With the Altera (quartus) tool, I was able to completely script
(tcl) the
> > synthesis flow.  Just run a few scripts (like synopsys) to do the
job.  No
> > interactive stuff, no display stuff !  Automatisation and batch
runs, a real
> > need in a good design flow !
> > But how about scripting in the foundation toolset ?  Is it not
possible ?
> > And what about the Alliance toolset ?  Synplify as precompiler,
perfect
> > (synplify does support scripting) but I would like to script the
total flow.
> >
> > So, after desparately surfing the Xilinx website, is there anybody
who knows
> > how to do scripting with the Xilinx tools ?
> >
> > regards,
> >
> > Peter
>
> --------------30802F542B8914A23CAC4176
> Content-Type: text/x-vcard; charset=us-ascii;
>  name="brian.philofsky.vcf"
> Content-Transfer-Encoding: 7bit
> Content-Description: Card for Brian Philofsky
> Content-Disposition: attachment;
>  filename="brian.philofsky.vcf"
>
> begin:vcard
> n:Philofsky;Brian
> tel;work:1-800-255-7778
> x-mozilla-html:TRUE
> url:http://www.xilinx.com
> org:Xilinx, Inc.;Software Marketing
> adr:;;2300 55th Street;Boulder;CO;80301;USA
> version:2.1
> email;internet:brianp@xilinx.com
> title:Sr. Technical Marketing Engineer
> fn:Brian Philofsky
> end:vcard
>
> --------------30802F542B8914A23CAC4176--
>
>


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Article: 26534
Subject: Re: scripting with xilinx tools (foundation) ????
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Thu, 19 Oct 2000 12:23:59 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------BF8B9D8A625493E1CBD0FF27
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



erika_uk@my-deja.com wrote:

> why is the the benefit from using  Script command file

If I understand the question, I believe you are asking why use xflow when
you can write you own script file to execute the various flow programs
(ngdbuild, map, par, etc.)?  There can be a few answers to that question.
First off, xflow is a single command that does not require the user to have
specific knowledge of the underlying FPGA/CPLD design flow or have any real
particular knowledge of scripting languages.  In general it is simpler to
use than writing a script of the flow yet gives you power to flip any switch
and customize your design flow as needed. Also, since it is a Xilinx created
and supported program, it gets updates with each release to reflect any
possible changes that may incur during a new software release.  In other
words, your command lines and scripts do not usually need to change from
software release to release.  It can make maintenance a bit easier.

If you are happy writing and using your own script to execute the various
Xilinx flow programs then that is absolutely fine.  This is just another
tool in your bag that may make it easier for some/most to use the Xilinx
software.  I use to use my own CSH scripts to process the design however I
have long abandoned my scripts since xflow came along.  To each his own
though.


--  Brian



>
> In article <39EE31D1.16735214@xilinx.com>,
>   brian.philofsky@xilinx.com wrote:
> > This is a multi-part message in MIME format.
> > --------------30802F542B8914A23CAC4176
> > Content-Type: text/plain; charset=us-ascii
> > Content-Transfer-Encoding: 7bit
> >
> > Hello Peter,
> >
> >      There is a command-line command called xflow which will take an
> EDIF file
> > and run it through the the Xilinx tools including bitstream creation
> and
> > simulation file creation.  Xflow is availible in Foundation, Alliance
> and ISE
> > packages.  You can run this command from a TCL script in Synplfy (or
> FPGA
> > Express or Leonardo or Modelsim or any TCL interface) if you wish
> using the
> > "exec" command, you can run it from a batch/shell script, or just type
> it on the
> > command-line.  You can run it with all default settings or customize
> the varoius
> > switches and design flow.  It is pretty simple to use and learn.  I
> find this
> > much easier to use than the TCL interface with Quartus and I am sure
> you will as
> > well once you get to know it a bit.
> >
> >     Complete documentation on xflow can be found at:
> >
> http://toolbox.xilinx.com/docsan/3_1i/data/common/dev/chap22/dev22000.ht
> m
> >
> >    Hope this works for you.
> >
> > --  Brian
> >
> > peter wrote:
> >
> > > Hi,
> > >
> > > As an asic designer, I used altera components for prototyping
> (realtime
> > > functional verification of subblocks) in the past.  Currently (new
> job), we
> > > are using the Xilinx environment.
> > > With the Altera (quartus) tool, I was able to completely script
> (tcl) the
> > > synthesis flow.  Just run a few scripts (like synopsys) to do the
> job.  No
> > > interactive stuff, no display stuff !  Automatisation and batch
> runs, a real
> > > need in a good design flow !
> > > But how about scripting in the foundation toolset ?  Is it not
> possible ?
> > > And what about the Alliance toolset ?  Synplify as precompiler,
> perfect
> > > (synplify does support scripting) but I would like to script the
> total flow.
> > >
> > > So, after desparately surfing the Xilinx website, is there anybody
> who knows
> > > how to do scripting with the Xilinx tools ?
> > >
> > > regards,
> > >
> > > Peter
> >
> > --------------30802F542B8914A23CAC4176
> > Content-Type: text/x-vcard; charset=us-ascii;
> >  name="brian.philofsky.vcf"
> > Content-Transfer-Encoding: 7bit
> > Content-Description: Card for Brian Philofsky
> > Content-Disposition: attachment;
> >  filename="brian.philofsky.vcf"
> >
> > begin:vcard
> > n:Philofsky;Brian
> > tel;work:1-800-255-7778
> > x-mozilla-html:TRUE
> > url:http://www.xilinx.com
> > org:Xilinx, Inc.;Software Marketing
> > adr:;;2300 55th Street;Boulder;CO;80301;USA
> > version:2.1
> > email;internet:brianp@xilinx.com
> > title:Sr. Technical Marketing Engineer
> > fn:Brian Philofsky
> > end:vcard
> >
> > --------------30802F542B8914A23CAC4176--
> >
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

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Content-Type: text/x-vcard; charset=us-ascii;
 name="brian.philofsky.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Philofsky
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begin:vcard 
n:Philofsky;Brian
tel;work:1-800-255-7778
x-mozilla-html:TRUE
url:http://www.xilinx.com
org:Xilinx, Inc.;Software Marketing
adr:;;2300 55th Street;Boulder;CO;80301;USA
version:2.1
email;internet:brianp@xilinx.com
title:Sr. Technical Marketing Engineer
fn:Brian Philofsky
end:vcard

--------------BF8B9D8A625493E1CBD0FF27--


Article: 26535
Subject: Re: How safe is the algorithm implemented with FPGA?
From: nweaver@soda.CSUA.Berkeley.EDU (Nicholas Weaver)
Date: 19 Oct 2000 18:59:11 GMT
Links: << >>  << T >>  << A >>

	I swear, this should be a faq.

	Design protection in an SRAM based FPGA really depends on your
level of paranoia.

	The standard route, where the device is programed from an off
chip ROM, is trivially easy to copy the bitfile, just desolder the ROM
and read it out.  Security mechanisms short of an FPGA with a built in
unique key and decryption circuitry don't really work, as it basically
comes down to capturing the bitstream as it is read into the FPGA.

	Even a very naive opponent can capture & copy your netlist.
Going beyond that to decompiling and reverse engineering is just time
& effort.

	ASICs are harder to disassemble, but not THAT hard.  It takes
more time & effort to capture the netlist, but this is a well
understood process.  There are obsfucation techniques, but they aren't
prefect.

	The ultimatly paranoid approach of configuring the FPGA once
and keeping it powered all the time, is the hardest for the attacker
to capture the netlist.  There ARE techniques for delidding and
examining a running chip, so even this is not perfect, but is
definatly the hardest/most expensive to accomplish.

	Of course, if the device ever loses power it
has to be returned to you to be reprogramed, which may be a
SIGNIFICANT inconvenience/limitation.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 26536
Subject: DS2401 security from pirating an FPGA
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Thu, 19 Oct 2000 19:35:41 GMT
Links: << >>  << T >>  << A >>
Hi,

This security method can be broken by replicating the serial number.

How much more secure would it be to not only check the serial number but
also check the timing. For example: read it a bit too slow and a bit too
fast and expect it to fail. If it passes, it must be a copy stored in some
other device with different timing ?

Does every purchaser of the DS2401 get a unique number ?? How could this be
??

If I buy 100 and later buy another 100 how will they have the same serial
number ??

How would they know how many to produce with each number ?

Makes it sound like each one is unique. This means every FPGA board must be
reprogrammed to look for a unique number. Is this the case ?

Dan






Article: 26537
Subject: Re: Q: Xilinx unified libraries and synthesis
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 19 Oct 2000 13:18:45 -0700
Links: << >>  << T >>  << A >>
Franz Hollerer wrote:
> 
> Hi!
> 
> I want to use the Xilinx unified libraries for a design but I have
> trouble to
> synthesize the design.
> 
> FPGA: Xilinx Virtex XCV50
> VHDL synthesis tool: Synopsys FPGA Express 3.3.0.4517 (comes with
> Viewlogic)
> Xilinx Software: Xilinx Alliance Series 2.1i
> 
> I managed to simulate the design using UNISIM. I believe I also need
> this library for synthesis. Is this true?
> 
> I tried to analyse the vhdl files for the UNISIM library with FPGA
> express.
> But I failed to analyse unisim_VPKG.vhd. FPGA Express stops with errors:
> 
>    VITALTABLESYMBOLTYPE is not declared. (VSS-575)
> (FPGA-dm-hdlc-unknown)
> 
> What I am doing wrong? I read the Xilinx "Synthesis and Simulation
> Design Guide". But I can't get
> the STARTBUF example to work.
> I looked at the UNISIM vhdl sources where I found some translation_off
> and translation_on
> pragmas. Thus I think unisim is thought for synthesis too. Which means I
> must manage to
> build the unisim library with FPGA express. Right?

If you need to use the unisim library to functionally simulate your
design, you need to include the

library unisim;
use unisim.VCOMPONENTS.all;

clauses in your code.  The unisim library should not be compiled for
synthesis, so what happens is that the synth tool complains about "can't
find libary unisim" or some such when it tries to compile your source. 
To solve that, put translate_off/translate_on pragmas around the library
reference:

-- synopsys translate_off
library unisim;
use unisim.VCOMPONENTS.all;
-- synopsys translate_on

That'll stop FPGA Express from complaining about libraries it doesn't
need.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26538
Subject: Re: VHDL vs Verilog
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 19 Oct 2000 13:26:09 -0700
Links: << >>  << T >>  << A >>
Muzaffer Kal wrote:
> 
> Ray Andraka <ray@andraka.com> wrote:
> 
> >I don't think there is such a thing as neutral ground when it comes to that
> >subject.  It is more like religion.  That said, I use VHDL because it gives me
> >more control for getting the design to exactly what I want.  It is more verbose
> >than verilog, and can be more difficult to master (according to some).  However,
> >it has the controls I need to be able to do placement from within the code, and
> >use it as a generator as opposed to for synthesis.  As of last year, you
> >couldn't do everything I needed with verilog.
> 
> Ray,
> would you like to expand little bit on what things VHDL does better
> for you ?

Here's my take on it.  I had a Verilog refresher yesterday.

VHDL forces you to think more about what you're trying to accomplish. 
It's verbose, but by being verbose, things are clearly specified.

Also, Verilog gives you enough rope to hang yourself.  For instance, it
allows you to connect things (vectors, ports, etc) with mismatched
sizes.  If the source port is narrower than the destination port, the
extra bits in the destination are filled with zeros.  If the source port
is wider than the destination, the extra bits are truncated!

VHDL, of course, says, "What are you, nuts?  Your ports must be the same
size."

I could go on, but I'm tired.  Software crash at the Los Angeles
flight-control center delayed my flight this morning.  They must have
been running Windows ME, or something.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26539
Subject: PCI Core : Clock Problem
From: "Walter Haas" <walter_haas@pmc-sierra.com>
Date: Thu, 19 Oct 2000 13:29:01 -0700
Links: << >>  << T >>  << A >>
I'm using the PCI core from Xilinx, and I'm having some problems when I try to synthesize with Synplify Pro.

This problem comes in two parts:

1) Because the core is a Black Box, Synplify doesn't know that it has it's own pads and especially it's own Global Clock. I usually have to edit out the pad and buffer it instantiates for the core from the EDF netlist, and that
usually works. It's a pain in the ass though, and I only seem to see it sporadically. Anyone know the cause?

2) The output (and globally buffered) clock from the PCI core is a clock I use extensively in my design. However, because Synplify doesn't know that it's globally buffered, it inserts more buffers all over the place, which in turn makes the Xilinx Skew analysis puke. Anyone know how to solve this?

This posting is mirrored on the xilinx general newsgroup, as well as news.synplicity.com, on the synplicity.synplify. I'm a bit of a newbie when it comes to newsgroups...

Cheers,

Wally

Article: 26540
Subject: Re: How safe is the algorithm implemented with FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 19 Oct 2000 21:02:05 GMT
Links: << >>  << T >>  << A >>
Ahh, the perennial design security question.  If you are worried about an
outright copy, SRAM fpga bitstreams are easy to intercept and copy in current
devices.  For a the guy who wants to copy your design exactly, it is easily
done.  You can make it harder by using unmarked or custom markings on the
device, and requiring the device to interact with other elements in the system
that may be harder to copy the board design (like a micro with an embedded
instruction store).  If you do that, don't use a serial EPROM fro programming, 
those are a dead givaway that the mystery device is an FPGA.  If you use the
VIrtex parts and the select map interface, it is a little less obvious it is an
FPGA (the old standard interface is very obvious if you stick an oscilloscope on
the din or CCLK pins.

If you put some identifiers in the design, outright copies are easily identified
which at least lets you prove ownership.  Of course you have to catch the
counterfeiter first.

Reverse engineering a bitstream is quite a bit more work.  As of now, the
bitstream formats are not really published, so in order to do anythng with the
bitstream, you first have to figure out the meanings of each bit.  It is
certainly doable, but it is not a trivial task.  Tools like JBITs give a little
more visibility into the bitstream structure, so they could conceivably make the
job marginally easier.  Still, it is a rather large effort.  Once you do
decipher a given bitstream, you still have to reverse engineer the ratsnest of
connected luts and flip-flops to grok the function.  Remember the bitstream is a
flat primitive level representation of the design.  It can be quite a chore to
reassemble the design into an understandable format from that, especially now
that the device sizes have gotten so large.  For an idea of what reverse
engineering a recovered flat netlist would be, take a VHO file (the back
annotated timing simulation netlist) from the tools and figure out what it
does.  It can be done, but it takes alot of patience and time to accomplish.

The question you must ask yourself if what would the recovered design be worth
to someone, how much is that  effort worth?  If you need utmost security, you
could battery back the FPGA and leave it powered romless in some applications. 
I've done it for some military applications where the FPGA gets loaded before a
mission.  I wouldn't use this in a consumer application though, it wouldn't be
worth the headache for servicing units with dead batteries or that had been
glitched for some reason.

My final point is, if the design you are protecting is worth enough to someone,
there is really nothing you can do to provide 100% security, whether it is an
FPGA, and AsiC, or a microcontroller.

Yu Chen wrote:
> 
> Hi, there,
> 
> I'd like to know more about this topic:
> How safe is the algorithm which is implemented using Altera's products? I mean, in case someone less got the FPGA(or ASIC)with the algorithm coded in it and he wanted to steal the algorithm, how much effort is needed for him to get the algorithm or just duplicate another FPGA( or ASIC) with the same function? We are thinking about using Altera's product to protect our own algoithms from being stolen. Please also let me know where I could get more information about this.
> 
> Thank you in advance.
> Yu Chen

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26541
Subject: Re: DS2401 security from pirating an FPGA
From: Ray Andraka <ray@andraka.com>
Date: Thu, 19 Oct 2000 21:05:52 GMT
Links: << >>  << T >>  << A >>
you can order many with the same number.  Part of the serial number is a
manufacturer ID that is unique to a customer.  The rest is specified by the
customer.  The problem with a DS2401 is that it is trivial to capture the serial
number, and then that is easy to duplicate with a CPLD.  The timing spec on
those is pretty loose to make sure they work in your application. It is easy to
duplicate the timing within the tolerance of the part.

Dan wrote:
> 
> Hi,
> 
> This security method can be broken by replicating the serial number.
> 
> How much more secure would it be to not only check the serial number but
> also check the timing. For example: read it a bit too slow and a bit too
> fast and expect it to fail. If it passes, it must be a copy stored in some
> other device with different timing ?
> 
> Does every purchaser of the DS2401 get a unique number ?? How could this be
> ??
> 
> If I buy 100 and later buy another 100 how will they have the same serial
> number ??
> 
> How would they know how many to produce with each number ?
> 
> Makes it sound like each one is unique. This means every FPGA board must be
> reprogrammed to look for a unique number. Is this the case ?
> 
> Dan

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26542
Subject: Re: How safe is the algorithm implemented with FPGA?
From: nweaver@soda.CSUA.Berkeley.EDU (Nicholas Weaver)
Date: 19 Oct 2000 21:13:18 GMT
Links: << >>  << T >>  << A >>
In article <39EF6136.D67121DD@andraka.com>,
Ray Andraka  <ray@andraka.com> wrote:
> certainly doable, but it is not a trivial task.  Tools like JBITs
> give a little more visibility into the bitstream structure, so they
> could conceivably make the job marginally easier.

	Nudge Nudge, wink wink, java decompilers are really good, as
Xilinx people have told me, although this was with respect to coregen
and not jbits.

> My final point is, if the design you are protecting is worth enough
> to someone, there is really nothing you can do to provide 100%
> security, whether it is an FPGA, and AsiC, or a microcontroller.

	The simple lesson:  "There is no such thing as a trusted box
in untrusted hands".
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 26543
Subject: CoolRunner news :(
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Thu, 19 Oct 2000 14:16:40 -0700
Links: << >>  << T >>  << A >>
Discontinuation notice here:
http://www.xilinx.com/partinfo/notify/pdn0007.htm

Looks like everything but the XPLA3 family goes.
Last time buy April 27/01.

-- 
Tom Burgess 
Digital Engineer
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Article: 26544
Subject: Re: PCI Core : Clock Problem
From: Carl Rohrer <carl.rohrer@xilinx.com>
Date: Thu, 19 Oct 2000 15:43:09 -0600
Links: << >>  << T >>  << A >>
Hi Wally,

I posted this answer on your forum query but I'll post it here too.

Check out the implementation guide.  You'll find step by step instructions for Synplicity.  Synplify Pro is not one of the supported flows but I would think it is similar enough to Synplicity to work the same.

The guide is in the docs directory when you download the core.

Regards,
Carl




Walter Haas wrote:

> I'm using the PCI core from Xilinx, and I'm having some problems when I try to synthesize with Synplify Pro.
>
> This problem comes in two parts:
>
> 1) Because the core is a Black Box, Synplify doesn't know that it has it's own pads and especially it's own Global Clock. I usually have to edit out the pad and buffer it instantiates for the core from the EDF netlist, and that
> usually works. It's a pain in the ass though, and I only seem to see it sporadically. Anyone know the cause?
>
> 2) The output (and globally buffered) clock from the PCI core is a clock I use extensively in my design. However, because Synplify doesn't know that it's globally buffered, it inserts more buffers all over the place, which in turn makes the Xilinx Skew analysis puke. Anyone know how to solve this?
>
> This posting is mirrored on the xilinx general newsgroup, as well as news.synplicity.com, on the synplicity.synplify. I'm a bit of a newbie when it comes to newsgroups...
>
> Cheers,
>
> Wally


Article: 26545
Subject: Very Lucrative FPGA Jobs
From: "Edwin" <itjobs1@hotmail.com>
Date: Thu, 19 Oct 2000 18:51:44 -0400
Links: << >>  << T >>  << A >>
Our client is looking for FPGA(Field Programmable Gate Array) designers to
work on a major effort to become the embedded technology supplier of choice
for the world's leading telecommunications and networking companies.  The
project is part of the effort to utilize FPGA designers to help develop a
new line of CPU boards, communication interfaces such as T1/E1 spans or fast
serial ports) and protocol subsystems that can be sold off the shelf to
customers so that their internal engineers and designers can utilize these
platforms that will be used to develop chips to be used in mobile phones and
telecommunications equipment.

Day-to-Day Responsibilities:

Consultants or FPGA Designers (Field Programmable Gate Array) will be
involved with designing Programmable Logic Chips, otherwise known as PLD's.
These PLD's make up a high density field of gates called FPGA Architectures.
The FPGA designers will be involved with designing a "gate array" which is
an unfinished chip with electronic components that have not yet been
connected.  The designer will complete the chip by designing and adhering
the top metal layers which provide interconnecting pathways.    Once these
chips are designed, then they will be turned over to manufacturing for mass
production.  These chips will make up final products such as CPU boards,
communication interfaces, and protocol subsystems that will be used in the
telecommunications industry.
There are a total of 9 groups for that have anywhere from 4 to 14 FPGA
designers and Hardware Engineers that are working on the 3 major products
for different customers.  Submitted candidates will be placed in groups that
need the most help.  This is a cross functional project environment.
Candidates will always work under a principal engineer.  FPGA designers will
track their performance and product development with Microsoft Project that
will be reported to the head engineer.

Essential Skills:

Power PC
PCI Hardware and Software
VHDL
Embedded Hardware Design
3 years experience in the industry


Plus Skills:

View Logic (Schematic Capture Product)
Simulation Experience (Signal Quality or Timing Simulation experience)
UNIX Experience
Telecom Experience (T1/E1 Interfaces)



Article: 26546
Subject: Virtex E development boards
From: "Domagoj" <domagoj@engineer.com>
Date: Fri, 20 Oct 2000 01:16:09 +0200
Links: << >>  << T >>  << A >>
Hi,
    I'm looking for Virtex E development boards. I had a look on
http://www.xilinx.com/products/protoboards/protoboards.htm
but couldn't find any company offering what I'm looking for.

Any recomendations ?

Thanks. Regards,

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------



Article: 26547
Subject: FPGA Designers Wanted!!!!!
From: "Edwin" <itjobs1@hotmail.com>
Date: Thu, 19 Oct 2000 19:20:35 -0400
Links: << >>  << T >>  << A >>
email: itjobs1@hotmail.com (sorry about the bad email)


Our client is looking for FPGA(Field Programmable Gate Array) designers to
work on a major effort to become the embedded technology supplier of choice
for the world's leading telecommunications and networking companies.  The
project is part of the effort to utilize FPGA designers to help develop a
new line of CPU boards, communication interfaces such as T1/E1 spans or fast
serial ports) and protocol subsystems that can be sold off the shelf to
customers so that their internal engineers and designers can utilize these
platforms that will be used to develop chips to be used in mobile phones and
telecommunications equipment.

Day-to-Day Responsibilities:

Consultants or FPGA Designers (Field Programmable Gate Array) will be
involved with designing Programmable Logic Chips, otherwise known as PLD's.
These PLD's make up a high density field of gates called FPGA Architectures.
The FPGA designers will be involved with designing a "gate array" which is
an unfinished chip with electronic components that have not yet been
connected.  The designer will complete the chip by designing and adhering
the top metal layers which provide interconnecting pathways.    Once these
chips are designed, then they will be turned over to manufacturing for mass
production.  These chips will make up final products such as CPU boards,
communication interfaces, and protocol subsystems that will be used in the
telecommunications industry.
There are a total of 9 groups for that have anywhere from 4 to 14 FPGA
designers and Hardware Engineers that are working on the 3 major products
for different customers.  Submitted candidates will be placed in groups that
need the most help.  This is a cross functional project environment.
Candidates will always work under a principal engineer.  FPGA designers will
track their performance and product development with Microsoft Project that
will be reported to the head engineer.

Essential Skills:

Power PC
PCI Hardware and Software
VHDL
Embedded Hardware Design
3 years experience in the industry


Plus Skills:

View Logic (Schematic Capture Product)
Simulation Experience (Signal Quality or Timing Simulation experience)
UNIX Experience
Telecom Experience (T1/E1 Interfaces)



Article: 26548
Subject: Re: Very Lucrative FPGA Jobs
From: "Austin Franklin" <austin@darkroo99.com>
Date: 20 Oct 2000 00:22:40 GMT
Links: << >>  << T >>  << A >>
> Consultants or FPGA Designers (Field Programmable Gate Array) will be
> involved with designing Programmable Logic Chips, otherwise known as
PLD's.
> These PLD's make up a high density field of gates called FPGA
Architectures.
> The FPGA designers will be involved with designing a "gate array" which
is
> an unfinished chip...

Now, do you REALLY think someone would be qualified to do this job if you
had to explain this to them...especially like this?



Article: 26549
Subject: Hay Ray -
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 20 Oct 2000 00:36:48 GMT
Links: << >>  << T >>  << A >>
My timing verification idea was not clear.

I suggest reading the stream over and over again repeatedly at different
speeds to search for the failure speed. The DS2401 has a maximum speed in
the 16.3Kbps range. If you can read the stream at 120% of max bandwidth then
it must be a copy in a faster device.

A pirate would not think about replicating the bandwidth
Just how robust is this timing security method ?



Dan








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