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Messages from 64050

Article: 64050
Subject: Re: advantages of ethernet MAC ip core
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Sun, 14 Dec 2003 07:48:34 GMT
Links: << >>  << T >>  << A >>
No, I didn't use any PLL so far.
For receiving, I oversampled the signal (possible since 10BASE-T is so slow)
and for transmitting I used a 20MHz clock.
100BASE-T would surely have been more difficult, first the signal looks like
125MHz, and now you mention this 3 voltage signals...

I didn't use any transformer, used capacitive coupling for the receiver, and
direct coupling for the transmitter... works in the lab!
A transformer might be necessary in real life for security or reliability
reasons?
Jean

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:RyTCb.387078$ao4.1285856@attbi_s51...
> (snip question about ethernet in FPGA)
>
> Jean Nicolle wrote:
>
> > Actually, if you accept a few restrictions, you can do it all in the
FPGA
> > with very little outside electronics.
> > I've got good success with 10BASE-T
> > http://www.fpga4fun.com/10BASE-T.html
>
> Do you need a PLL to do it?  I thought it would, but maybe not.
>
> For 100baseTX you need three voltage levels.  Maybe two outputs and
> appropriate resistors would work.   Detecting three voltages on input
> will be hard, though.
>
> You still need the transformer, which usually doesn't come in
> an FPGA.
>
> -- glen
>



Article: 64051
Subject: multiplier,CLK-insufficient RECOVERY time after async CLEAR
From: dxyyjb@sohu.com (ranbow)
Date: 14 Dec 2003 03:58:20 -0800
Links: << >>  << T >>  << A >>
hello, 
when i do timing simulation with multiplier(WHETHER the one generated
by the CORE generator system OR the macro created by the vhdl source
file),such error messages always appear:

Simul:10.9ns:H1/U3/product_reg<7>.CLK-insufficient RECOVERY time after
async CLEAR,missing time 1.6ns

Simul:90.9ns:H1/U3/product_reg<2>.IN-too short SETUP time,missing time
1ns


i can't see why i am getting these error messages.
Can anyone help me?

Article: 64052
Subject: Re: advantages of ethernet MAC ip core
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Sun, 14 Dec 2003 13:20:14 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Sun, 14 Dec 2003 07:48:34 GMT) it happened "Jean Nicolle"
<j.nicolle@sbcglobal.net> wrote in
<mBUCb.71275$Q%5.12131@newssvr25.news.prodigy.com>:

>No, I didn't use any PLL so far.
>For receiving, I oversampled the signal (possible since 10BASE-T is so slow)
>and for transmitting I used a 20MHz clock.
>100BASE-T would surely have been more difficult, first the signal looks like
>125MHz, and now you mention this 3 voltage signals...
>
>I didn't use any transformer, used capacitive coupling for the receiver, and
>direct coupling for the transmitter... works in the lab!
>A transformer might be necessary in real life for security or reliability
>reasons?
>Jean
I have also build that little differential amp from fpga-fun site.
Not all working yet (no time).
I have not looked up the 100BASE-T spec yet, but 3 voltage levels can
be done using 2 banks with 2 different references?
For a 100MHz transformer, remember those 300Ohm to 75 coax VHF
transformers?
Every old TV had one, just a ferrite core with 3 or 4 turns...
But my ethernet card was only 5.80 Euro, (6 $), there is a small
transformer on it.
So for 6 $ you have a transformer.
Dunno how they can make these cards for that price.
J

Article: 64053
Subject: Help w/ WARNING:Xst:1868
From: "Ed Anuff" <ed@anuff.com>
Date: Sun, 14 Dec 2003 15:32:51 -0800
Links: << >>  << T >>  << A >>
I'm seeing the following in my synthesis report in ISE 6.1: 
WARNING:Xst:1868 - You have explicitly defined initial contents for this RAM, which are currently ignored when the RAM is dual-port, leading to incorrect circuit behavior. 

What does this mean? Does it mean that initial values for dual port block ram is not supported?



Article: 64054
Subject: Re: Q:Altera's excalibur device
From: algous2002@yahoo.com.cn (algous)
Date: 14 Dec 2003 17:02:38 -0800
Links: << >>  << T >>  << A >>
hi Mike,
   At present, the function and timing simulating are all well. data
translated as expectation.
           

"Mike Lewis" <someone@microsoft.com> wrote in message news:<MsqdnTiwDoZz_0qiRVn-sQ@magma.ca>...
> Did you try simulating the problem to see if
> you can get more information. Your description
> of the problem is rather high level.
> 
> Mike
> 
> "algous" <algous2002@yahoo.com.cn> wrote in message
> news:1e71fcd5.0312081757.40fea000@posting.google.com...
> > Dear all,
> >    I implement a DMA controller in the PLD side of the ALtera's
> > excalibur device(epxa1), and a block ram in the PLD other. DMA
> > controller access data through the PLD-to-STRIP bridge. I config the
> > DMA controller through STRIP-to-PLD bridge.
> >    now I need to exchange datas between the sdram(out of chip) and the
> > RAM in PLD. It seemed that some datas not translated successly, there
> > would be eight continual beats failed every since. while other datas
> > sucessful, and there would be eight continual beats as well.
> >   The DMA controller was designed refer to ALtera's "AN 287: Using
> > Excalibur DMA Controllers for Video Imaging ". I dont confirmed the
> > AN287 is ok, I thinked it's worked well.
> >   In the other hand, If the DMA controller exchange between the
> > SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA
> > controller worked very well. The timing and function simulation is
> > successed as well.
> >   I think if there were some bugs in the excliabur device. The above
> > sympton seemd is related with the SDRAM' controller or the AHB BUS.
> > because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers
> > to the memory are made up of eight-beat reads and writes. A request
> > from the system bus that does not map directly to this fixed-beat
> > access(for example, A larger burst size  or a wrapping transfer) is
> > handled by performing multiple accesses. Burst termination is utilized
> > to maximize throughput."
> >
> > regards
> >
> > algous

Article: 64055
Subject: Re: VHDL-Testbench-Simulation in QuartusII
From: ALuPin@web.de (ALuPin)
Date: 14 Dec 2003 23:50:14 -0800
Links: << >>  << T >>  << A >>
> In this case rename your vhd file which contains the testbench to the .vht
> extension using the Windows Explorer or DOS prompt.
> 
> - Subroto

Hi,

are the following settings right ?


Settings --> EDA Tool Settings --> Advanced VHDL Simulation Options

--> Test Bench Mode:  Test Bench File:         ...tb_reservoir_positions.vht
                      Test Bench entity name:  ...tb_reservoir_positions.vht



reservoir_positions.vhd is the module to be simulated (and therefore
it is instantiated in the testbench tb_reservoir_positions.vht)

There seems to be some problem with it because after compiling I get the
following error messages:

- Error: Compilation of design file Reservoir_positions.vho was NOT successful
- ModelSim couldn't execute "vcom": no such file or directory
- Error: Compilation of test bench file ... tb_reservoir_positions.vht was NOT
  successful
- Error: Simulation of design tb_reservoir_positions.vht was NOT successful

Thanks
Andre V.

Article: 64056
Subject: Re: byte order microblaze
From: "Frank" <someone@work.com>
Date: Mon, 15 Dec 2003 08:57:48 +0100
Links: << >>  << T >>  << A >>
I also tested the same code with a pointer to bram, that was working good (I
got the expected output). I am using the Virtex II development board. I will
check the connections.

Thanks,
Frank

"Anita Schreiber" <anitas@xilinx.com> wrote in message
news:3FDA3B4A.E206AF06@xilinx.com...
> Frank,
>
> I've also used char in my code when testing the OPB SDRAM controller and
not
> seen a problem.
>
> There is a bit-ordering difference that is really only important in the
address
> bus simply because when setting the SDRAM mode register, the address bus
> contains the data for that register.
>
> So I reccommend checking the bit-ordering connections. There are some
examples
> in the design spec.
>
> Thanks!
> anita
>
> Vasanth Asokan wrote:
>
> > I have this piece of code. I have just used char instead of BYTE. I get
> > the proper output. I do not see the interleaving that you specify.
> > If you can give more info about the design you are seeing this problem
> > with, we can take a look.
> >
> > =====
> > int main()
> > {
> >     static volatile char * const p_sdram = (char *) 0xe000000;
> >     int i;
> >
> >     for (i = 0; i < 16; i++) {
> >         *(p_sdram+i) = i;
> >     }
> >
> >     for (i = 1; i <= 16; i++) {
> >         xil_printf("%02X ", (char) *(p_sdram+i-1));
> >     }
> >
> >     while (1);
> > }
> > ======
> >
> > Frank wrote:
> >
> > >Hi,
> > >
> > >I've a small program in bram which has a pointer to sdram.
> > >
> > >static volatile BYTE * const p_sdram = (BYTE *)
XPAR_SDRAM_CTRL_BASEADDR;
> > >
> > >in my code I try to fill the sdram (by the way, it's 32-bits wide
databus):
> > >
> > >for (i = 0; i < 16; i++) {
> > >    *(p_sdram+i) = i;
> > >}
> > >
> > >Now comes the problem: when I read back the data, each 2 bytes are
> > >exchanged. Reading back is done with the same byte pointer:
> > >
> > >for (i = 1; i <= 16; i++) {
> > >    xil_printf("%02X ", (BYTE) *(p_sdram+i-1));
> > >}
> > >
> > >The output is:
> > >
> > >01 00 03 02 05 04 07 06  09 08 0B 0A 0D 0C 0F 0E
> > >
> > >What is wrong?! If I have a byte pointer, the big or little endian
story
> > >doesn't matter, does it? I'm posting this here, because I have the
feeling
> > >that it has to do with the opb sdram controller? Can somebody explain
the
> > >above?
> > >
> > >Frank
> > >
> > >
> > >
> > >
>



Article: 64057
Subject: How LVDS Drivers kills?
From: naderimisc@yahoo.com (Masoud Naderi)
Date: 15 Dec 2003 00:37:38 -0800
Links: << >>  << T >>  << A >>
Dear all,
Please tell me how LVDS drivers with cables can damaged? 
Possible cases are:
1 - Power supply under/overshoots.
2 - ESD on cables.
3 - Missing hot-plugging. e.g. connect GND, then signal, then power.
4 - Killer spikes on power supply rail or input/outputs.
5 - ?

Regards.

Article: 64058
Subject: Re: Manufacturing Tests
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Mon, 15 Dec 2003 11:06:19 -0000
Links: << >>  << T >>  << A >>

Peter Alfke <peter@xilinx.com> wrote in message
news:3FD76B19.ACD26241@xilinx.com...
> Here is a general answer:
> Most manufacturers perform some degree of functional testing on the
> wafer, before it is divided into individual dice. The failing devices
> are marked with a red dot, and then dicarded after the wafer is divided.
> (Throwing bad devices away before packaging saves money, especially with
> large chips where the yield is significantly lower than 100%. The
> smallest devices are sometimes all packaged and tested as packaged
> parts.)

Peter,

Just out of interest, how is this done? Is a miniture
bed of nails test rig used or is extra functionality
designed into the wafer to allow test access to individual
die?


Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 64059
Subject: FLEX 10K50E, which software support it?
From: jaxlau@yahoo.com (Jacques athow)
Date: 15 Dec 2003 03:50:22 -0800
Links: << >>  << T >>  << A >>
I wanted to know which particular software from altera give support,
in terms of synthesis, P&R and downloading to this chip. Is the ALTERA
Max + Plus II suitable to program those chip?

And also, it seems that the 10K50E part is an obsolete part that has
been replaced by the 10K50S. Is there any difference between them, in
terms of implementation and bitstream compatibility?

Thanks for any help!
happy holidays

Article: 64060
Subject: Re: EDK, reset module, interrupts
From: Christian Haase <nospams@today.de>
Date: Mon, 15 Dec 2003 13:43:36 +0100
Links: << >>  << T >>  << A >>
Hello Frank and Paulo,

thanks for your replies. Your suggestions make my design run.

Christian


Article: 64061
Subject: Re: How LVDS Drivers kills?
From: "NJ" <aaa@msn.com>
Date: Mon, 15 Dec 2003 14:33:22 GMT
Links: << >>  << T >>  << A >>
Masoud,
    Can you tell me more about the failure mode?
NJ


"Masoud Naderi" <naderimisc@yahoo.com> wrote in message
news:2ba3bbea.0312150037.12810136@posting.google.com...
> Dear all,
> Please tell me how LVDS drivers with cables can damaged?
> Possible cases are:
> 1 - Power supply under/overshoots.
> 2 - ESD on cables.
> 3 - Missing hot-plugging. e.g. connect GND, then signal, then power.
> 4 - Killer spikes on power supply rail or input/outputs.
> 5 - ?
>
> Regards.



Article: 64062
Subject: .elf to .bin file for microblaze
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Mon, 15 Dec 2003 16:51:53 +0100
Links: << >>  << T >>  << A >>
I have a stand alone application which I want to download into external
sdram at a microblaze system. In bram a kind of bootloader is running. I try
to download via xmodem a binairy application to sdram and then jump to it.
To convert the application from .elf to .bin I use mb-objcopy:

mb-objcopy -I elf32-microblaze -O binary appl.elf appl.bin

when I look at the binary file with an editor I see the following:

B8 00 00 18 80 00 00 00 B0 00 7F FF B8 08 FF FF
.
.

when I look at sdram (after downloading) I see the following (unsigned char
pointer used for reading out):

00 B8 18 00 00 80 00 00  00 B0 FF 7F 08 B8 FF FF
.
.

Is this correct of should it be exactly the same as the binairy file?? (I
read that the bram is big endian and if I read here, the contents is the
same as the binairy file of the bootloader, but how is it with sdram, what
is the microblaze expecting (big endian of coarse, I know), but is the
binairy file created with objcopy ready to copy it byte for byte to sdram or
do I have to reverse something?

Frank



Article: 64063
Subject: Re: Programming Altera MAX 7000E
From: gregs@altera.com (Greg Steinke)
Date: 15 Dec 2003 09:20:41 -0800
Links: << >>  << T >>  << A >>
Derek,
The key difference is that MAX 7000S devices are
in-system-programmable, whereas MAX 7000E devices are programmed in a
programming unit. Altera has the "Altera Programming Unit" and the
"Altera Stand-Alone Programmer" which plug into a PC for programming
these devices. An adapter plugs into these programmers and then
accepts the devices for programming. For example, if you are
programming an EPM7128E in an 84-pin PLCC package, you would use the
PLMJ7000-84 adapter.
For software you can use the MAX+PLUS II Programmer which comes with
the programming unit. Generally we would recommend Quartus II, but it
does not program these older MAX 7000E devices.

For more details, please look at the "Altera Programming Hardware Data
Sheet" on http://www.altera.com/literature/ds/dspghd.pdf.

Sincerely,
Greg Steinke
Altera Corporation
gregs@altera.com


Derek_SImmons@msn.com (Derek Simmons) wrote in message news:<14030831.0312111651.32511dc2@posting.google.com>...
> I came across a small surplus of Altera MAX 7000Es. On Altera's
> website I found information about how to program the Altera MAX 7000S.
> Is programming the MAX 7000E the same or does it require special
> equipment?
> 
> Thanks,
> Derek Simmons

Article: 64064
Subject: Re: VHDL-Testbench-Simulation in QuartusII
From: Bassman59a@yahoo.com (Andy Peters)
Date: 15 Dec 2003 09:22:38 -0800
Links: << >>  << T >>  << A >>
"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...

> 
> A VHDL Test Bench File is the same as a standard VHDL test bench file, saved
> with a .vht extension.
> 

Why do vendors insist on using non-standard extensions for VHDL (and
Verilog) source files?  (Altera's not the only one.)

Emacs, for example, knows that a .vhd file is VHDL and a .v file is
Verilog.  It doesn't know about a .vht file, unless I go and tell it. 
ModelSim recognizes .vhd and .v files but doesn't know from .vht
files.

The solution, of course, is to rename the files created by the tools.

FWIW, I've adopted a simple notation to indicate that a file is a test
bench: given a module foo.vhd, its test bench is called foo_tb.vhd.

--a

Article: 64065
Subject: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 15 Dec 2003 10:37:11 -0800
Links: << >>  << T >>  << A >>
ranbow wrote:
> hello,=20
> when i do timing simulation with multiplier(WHETHER the one generated
> by the CORE generator system OR the macro created by the vhdl source
> file),such error messages always appear:
>=20
> Simul:10.9ns:H1/U3/product_reg<7>.CLK-insufficient RECOVERY time after
> async CLEAR,missing time 1.6ns
> =85=85=85=85=85=85=85=85
> Simul:90.9ns:H1/U3/product_reg<2>.IN-too short SETUP time,missing time
> 1ns
> =85=85=85=85=85=85=85=85
>=20
> i can't see why i am getting these error messages.

Sounds like you need to synchronize the reset pulse
in your testbench.

Did your design pass functional simulation
and static timing?

  -- Mike Treseler


Article: 64066
Subject: Re: Extracting timing from a demo board (V2MB1000)
From: Martin Kellermann <martin.kellermann@nospam.xilinx.com>
Date: Mon, 15 Dec 2003 19:39:38 +0100
Links: << >>  << T >>  << A >>
Hello,

if you have access to a Scope with a TDR (time domain reflectometer) you 
can get that information out...

Cheers,

Martin


PO Laprise wrote:

> Hello all, I'm trying to get a DDR SDRAM controller working reliably on 
> Insight/Memec's V2MB1000 development board, but I'm having some timing 
> issues.  I'm trying to correctly constrain my timing, and verify using 
> timing simulations, but I'm running into problems because I have no 
> information about the board delays between the memory and the FPGA.  I 
> especially need the clock feedback path delay (to set the DCM FEEDBACK 
> constraint), and the skew between the dqs lines and data (to know if I 
> can use dqs to latch data)
> 
> I don't have board layout information, and Insight/Memec hasn't yet 
> answered my requests (although, in their defence, it _has_ been less 
> than a week...), and I haven't found the info anywhere on their site or 
> in the provided documentation.  As far as probing is concerned, I only 
> have access to the memory's pins, so I'm not sure how I can determine 
> the delays from this.
> 
> So, what I was hoping to get is either suggestions about how I might 
> measure these delays, or, if someone has already measured/received this 
> information, the actual min:typ:max board delays between memory and FPGA.
> 
> Thanks a lot in advance!
> 


Article: 64067
Subject: Re: VHDL-Testbench-Simulation in QuartusII
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 15 Dec 2003 10:44:53 -0800
Links: << >>  << T >>  << A >>
ALuPin wrote:

> - ModelSim couldn't execute "vcom": no such file or directory
> - Error: Compilation of test bench file ... tb_reservoir_positions.vht was NOT
>   successful
> - Error: Simulation of design tb_reservoir_positions.vht was NOT successful

Consider vcom and vsim from the command line, not from Quartus.

  -- Mike Treseler


Article: 64068
Subject: Extracting timing from a demo board (V2MB1000)
From: PO Laprise <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca>
Date: Mon, 15 Dec 2003 18:45:46 GMT
Links: << >>  << T >>  << A >>
Hello all, I'm trying to get a DDR SDRAM controller working reliably on 
Insight/Memec's V2MB1000 development board, but I'm having some timing 
issues.  I'm trying to correctly constrain my timing, and verify using 
timing simulations, but I'm running into problems because I have no 
information about the board delays between the memory and the FPGA.  I 
especially need the clock feedback path delay (to set the DCM FEEDBACK 
constraint), and the skew between the dqs lines and data (to know if I 
can use dqs to latch data)

I don't have board layout information, and Insight/Memec hasn't yet 
answered my requests (although, in their defence, it _has_ been less 
than a week...), and I haven't found the info anywhere on their site or 
in the provided documentation.  As far as probing is concerned, I only 
have access to the memory's pins, so I'm not sure how I can determine 
the delays from this.

So, what I was hoping to get is either suggestions about how I might 
measure these delays, or, if someone has already measured/received this 
information, the actual min:typ:max board delays between memory and FPGA.

Thanks a lot in advance!

-- 
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --


Article: 64069
Subject: Re: Q:Altera's excalibur device
From: hbutler_at_altera@yahoo.com (Howard Butler @ Altera)
Date: 15 Dec 2003 10:47:47 -0800
Links: << >>  << T >>  << A >>
Hello,

Just for clarification, it sounds like you are attempting to design a
DMA controller in the FPGA of an Excalibur(XA)device and you are
currently having problems accessing SDRAM via the following path:

FPGA DMA -> PLD-to-Stripe Bridge -> AHB2 Bus -> SDRAM Controller AHB2
Slave interface-> Off chip SDRAM

It also sounds like you were SUCCESSFUL in accessing the embedded
stripe SRAM blocks via the following path:

FPGA DMA -> PLD-to-Stripe Bridge -> AHB2 Bus -> SRAM AHB2 Slave
interface -> Embedded Stripe SRAM.

If you are able to access SRAM successfully and are NOT able to access
SDRAM, problem is more than likely either in your SDRAM controller
setup, or a board level problem.


SDRAM Controller Setup:

With most SDRAM controllers there is some initial setup that has to
occur before you can access it properly.  The SDRAM controller in the
embedded stripe is no different.  The XA tool flow provides flow that
can make this very easy for you.  The last page of the stripe
megawizard is where the memory map for the device is configured.  In
addition, the configuration information for the SDRAM chips that your
using can be loaded.  There are several SDRAM chips that the stripe
megawizard knows about and you can just select the chip that you are
using.  If the chip that you are using isn't in the megawizard, then
you can add your own custom settings.  The parameters entered to the
wizard will eventually get passed to the XA bootloader and it will
configure the SDRAM controller for you according the parameters you
entered in the megawizard.  If you are not using the XA bootloader, or
just want to know what is involed in SDRAM configuration, AN141 Using
the SDRAM Controller, discusses details of SDRAM configuration.

You can get that here: http://www.altera.com/literature/an/an141.pdf
In addition, because SDRAM configuration is something that mostly done
during the boot process, I would recommend that you also have a look
at AN187 Booting Excalibur devices
http://www.altera.com/literature/an/an187.pdf.
  
Board Level Problem:

If you are not using a XA development board, then there is a
possiblity that you my have a board layout problem.  AN141 also gives
some basic SDRAM layout guidelines.

One common layout mistake people make with SDR and XA is not feeding
back the SD_CLK_N to the SD_DQS[0] pin.  See page 28 of AN141.  XA
SDRAM controller is both an DDR and SDR controller and in the SDR
configuration, SD_CLK_N needs to be feedback to SD_DQS[0].

One other thing you should look at:

So by being able to access SRAM it sounds like you are faily close to
getting your DMA to work.  One other thing you could consider is
downloading a SDRAM model for the chip you are using and attempt to
simulate your system.  AN192 has a SDR Micron model and shows both the
processor and a master in the FPGA accessing SDRAM.  So this will give
you a good proof of concept of SDRAM Access to look at.

You can get it here: http://www.altera.com/literature/an/an192.pdf. 
There are also design files which you can get from the top level of
the literture page:  http://www.altera.com/literature/lit-exc.jsp

Finally on the statement in the HRM: 

"Transfers
 to the memory are made up of eight-beat reads and writes. A request
 from the system bus that does not map directly to this fixed-beat
 access(for example, A larger burst size  or a wrapping transfer) is
 handled by performing multiple accesses. Burst termination is
utilized
 to maximize throughput."

This is basically referring to how the backend access to SDRAM are
made.  The SDRAM controller is going to buffer information that is
written/read when accessing the SDRAM controller.  The frequency and
amount of data retrived from SDRAM is going to depend on the type of
SDRAM configuration you have laided out on your board.  For
example...If you are interfacing to 16-bit sdram a request from XA
which is 32 bits will take multiple accesses to complete to account
for the mis-match in data widths.

I hope this helps...

God Bless
-Howard



algous2002@yahoo.com.cn (algous) wrote in message news:<1e71fcd5.0312081757.40fea000@posting.google.com>...
> Dear all,
>    I implement a DMA controller in the PLD side of the ALtera's
> excalibur device(epxa1), and a block ram in the PLD other. DMA
> controller access data through the PLD-to-STRIP bridge. I config the
> DMA controller through STRIP-to-PLD bridge.
>    now I need to exchange datas between the sdram(out of chip) and the
> RAM in PLD. It seemed that some datas not translated successly, there
> would be eight continual beats failed every since. while other datas
> sucessful, and there would be eight continual beats as well.
>   The DMA controller was designed refer to ALtera's "AN 287: Using
> Excalibur DMA Controllers for Video Imaging ". I dont confirmed the
> AN287 is ok, I thinked it's worked well.
>   In the other hand, If the DMA controller exchange between the
> SPRAM(single port RAM on chip) and the block ram in the PLD, the DMA
> controller worked very well. The timing and function simulation is
> successed as well.
>   I think if there were some bugs in the excliabur device. The above
> sympton seemd is related with the SDRAM' controller or the AHB BUS.
> because THE HARDWARE REFERENCE MANUAL's SDRAM section said "Transfers
> to the memory are made up of eight-beat reads and writes. A request
> from the system bus that does not map directly to this fixed-beat
> access(for example, A larger burst size  or a wrapping transfer) is
> handled by performing multiple accesses. Burst termination is utilized
> to maximize throughput."
> 
> regards
> 
> algous

Article: 64070
Subject: Re: Extracting timing from a demo board (V2MB1000)
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 15 Dec 2003 11:15:56 -0800
Links: << >>  << T >>  << A >>
PO Laprise wrote:

> So, what I was hoping to get is either suggestions about how I might 
> measure these delays, or, if someone has already measured/received this 
> information, the actual min:typ:max board delays between memory and FPGA.

Board delays are normally 1-2 nS which
should be much less than a clock period
which is the minimum wait for
a synchronous controller.

With a handshaking interface, you don't
need to measure the delays, you just
drive a READY wait for an ACK.

   -- Mike Treseler



Article: 64071
Subject: download ise foundation
From: "Norbert" <__kolek@interia.pl>
Date: Mon, 15 Dec 2003 21:27:16 +0100
Links: << >>  << T >>  << A >>
could you tell me where i can download xilinx ise foundation (version
unimportant)?
i couldn't find anything in the web. on xilinx website i can only order
foundation evaluation kit, but shipping and handling charges amount $20 and
i'm a poor student ;)

thanks for any help

Norbert
kolek@interia.pl



Article: 64072
Subject: Re: Soldering of FPGAs
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Mon, 15 Dec 2003 14:57:43 -0600
Links: << >>  << T >>  << A >>


Joel Smith wrote:

>Hello,
>
>Is it possible for a hobbyist to solder FPGAs with high pin counts to
>PCBs? How would I go about doing it? What equipment would I need?
>  
>
Yes.  You'd better have pretty good eyes and steady hands.

I am currently installing Xilinx XCS30TQ144 chips on a small production
product, that is the .5 mm lead pitch package.  I use solder paste, 
which I got in a 35 gm
syringe.  You will need to beg, borrow or steal (just kidding) needles 
around
20 gauge.  I cut them off fairly short, and then round the end off on a 
sharpening
stone so it is relatively free of scratchy edges and has a 30 degree or 
so slant
on the end.  You place the thinnest bead of solder paste on the outer 
edge of
the solder pads on the PCB.  You then position the chip with angled tweezers
and solder one corner lead, while trying to align the chip as well as 
possible
with the pads.  You go to the opposite corner and do another.  If necessary,
you may have to walk the chip slightly into better alignment.  When you have
all the pins reasonably well aligned, you just wipe the soldering tip 
along the
rows of pins, and the solder will flow into the joints.  If you use too much
solder, you will get bridges.  These are removed with solder wick.  When you
get it all soldered, apply rubbing alcohol to the chip and surrounding 
area, then
scrub very gently around the leads with a sift bristle toothbrush for a few
seconds.  Wash in water, then hit it with the blast from the kitchen spray
nozzle.  I then violently shake the board to drive off excess water.

The soldering iron should have temperature control, and a very small 
pointed tip.
I use either a Weller 1302 (old one) or the WSL with WMP iron (current 
model).

>I want to starting working with FPGAs and rather than buying a development
>board I wanted to build my own board gradually from scratch. Is this a
>silly idea?
>
>I've talked to some electrical repair people I know and they say its
>impossible to solder chips with 200 pins or so without expensive kit. Is
>this true? I could afford to spend maybe $100-$250 on some kit.
>  
>
Ahh, it is VERY difficult to REMOVE such chips with simple irons, etc.
It can be done, but is very time consuming.  On the other hand, the $40
package-specific desoldering heads can be adapted to some standard irons
to get a specific chip off cleanly.

If you don't want to save the chip, but the board, you can cut the leads 
off with an x-acto
knife, use tweezers to remove the leads, then desoldering braid to clean 
up.  You can also
use braid to remove the solder, then lift each lead one at a time, but 
that is really slow.

Jon


Article: 64073
Subject: Re: datasheet needed!
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 15 Dec 2003 12:58:26 -0800
Links: << >>  << T >>  << A >>
Sandor, that data sheet is from 1986. It, and the design of the chip is
18 years old. By my analogy of 1 FPGA-year = 15 human years, these parts
have an age of 270 human years. I cannot imagine why anybody would start
a new design with them.
There were no pdf files in 1986. I know there are printed data sheets,
but I really want to talk you out of this project. Spartan and Virtex
are so much more rewarding...
Peter Alfke
========================
Sandor Jager wrote:
> 
> Hi!
> I've bought a lot of XC2018 (yes I know, antic pieces),
> but they were very-veyr cheap, I've had no heart not to
> get them :)
> I'm looking for its complete datasheet, but I wasn't
> able to find it anywhere on the net...
> Has somebody got some point where to get it from, or
> maybe has a pdf ?...
> 
> Many thanx
> Sandor Jager

Article: 64074
Subject: Re: Soldering of FPGAs
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Mon, 15 Dec 2003 15:00:49 -0600
Links: << >>  << T >>  << A >>


Markus Zingg wrote:

>Your advice is perfectly ok, let me tell you though, that I'm
>regularly fabricating my own four layer PCB's at home.
>
Hey, I'd really like to hear about your multilayer process!  I have the gear
for 2-layer, but often just have them done by commercial shops.  But, I
could be real interested in any innnovative laminating and plating processes
you use!

Jon




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