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Messages from 64400

Article: 64400
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Thu, 01 Jan 2004 22:53:26 GMT
Links: << >>  << T >>  << A >>
On Thu, 1 Jan 2004 17:17:38 -0500, "Jerry" <nospam@nowhere.com> wrote:

>WOW, your prof let you use NANDs? we had to do this using only
>relays. Wish I had an easy prof like yours.
>
>(:>)
>
>Jer

Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
and levers!  Compared to that experience, designing with today's EDA
tools seems...well, pretty much the same, actually.

Bob Perlman
Cambrian Design Works



Article: 64401
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat>
Date: Thu, 01 Jan 2004 23:23:02 GMT
Links: << >>  << T >>  << A >>
On Thu, 01 Jan 2004 22:53:26 GMT, the renowned Bob Perlman
<bobsrefusebin@hotmail.com> wrote:

>On Thu, 1 Jan 2004 17:17:38 -0500, "Jerry" <nospam@nowhere.com> wrote:
>
>>WOW, your prof let you use NANDs? we had to do this using only
>>relays. Wish I had an easy prof like yours.
>>
>>(:>)
>>
>>Jer
>
>Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
>and levers!  Compared to that experience, designing with today's EDA
>tools seems...well, pretty much the same, actually.
>
>Bob Perlman
>Cambrian Design Works

You had gears and levers? We would have given our right arms for gears
and levers! Cowrie shells was what we had, and were glad for it. 


Best regards, 
Spehro Pefhany
-- 
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Article: 64402
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: Keith R. Williams <krw@attglobal.net>
Date: Thu, 1 Jan 2004 22:31:31 -0500
Links: << >>  << T >>  << A >>
In article <9d99vv0o606si8gvj10cgrsu35k1n011c4@4ax.com>, 
bobsrefusebin@hotmail.com says...
> On Thu, 1 Jan 2004 17:17:38 -0500, "Jerry" <nospam@nowhere.com> wrote:
> 
> >WOW, your prof let you use NANDs? we had to do this using only
> >relays. Wish I had an easy prof like yours.
> >
> >(:>)
> >
> >Jer
> 
> Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
> and levers!  Compared to that experience, designing with today's EDA
> tools seems...well, pretty much the same, actually.

Gag, spit, choke. Damn!  Don't *do* that!  Now I gotta clean of 
my monitor, again.

-- 
  Keith

Article: 64403
Subject: Re: Xilinx Parallel cable
From: Socrat <socrat@rogers.com>
Date: Fri, 02 Jan 2004 05:16:36 GMT
Links: << >>  << T >>  << A >>
Hi,

JTAG cable ,
$25 USD + same day shiping (~$3)
see at
www.seytronix.com

Regards!

Seiran

Sumit Gupta wrote:

> Hi
> 
> Is there is cheap source or alternative to Xilinx parallel cable ?
> 
> Also is it leagal to make my own cable (from the schemetic provided by
> Xilinx) and sell it.
> 
> Thanks
> Sumit


Article: 64404
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: John Woodgate <jmw@jmwa.demon.contraspam.yuk>
Date: Fri, 2 Jan 2004 05:34:34 +0000
Links: << >>  << T >>  << A >>
I read in sci.electronics.design that Jerry <nospam@nowhere.com> wrote
(in <vv973167vresd4@corp.supernews.com>) about 'SOS : 4-bit binary
divider circuit PLEASE!!!!!!!', on Thu, 1 Jan 2004:

>WOW, your prof let you use NANDs? we had to do this using only
>relays. Wish I had an easy prof like yours.

You were allowed RELAYS? We had to use frogs' legs. And catch the frogs
first.
-- 
Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk 
Interested in professional sound reinforcement and distribution? Then go to 
http://www.isce.org.uk
PLEASE do NOT copy news posts to me by E-MAIL!

Article: 64405
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: John Woodgate <jmw@jmwa.demon.contraspam.yuk>
Date: Fri, 2 Jan 2004 05:36:35 +0000
Links: << >>  << T >>  << A >>
I read in sci.electronics.design that Bob Perlman
<bobsrefusebin@hotmail.com> wrote (in <9d99vv0o606si8gvj10cgrsu35k1n011c
4@4ax.com>) about 'SOS : 4-bit binary divider circuit PLEASE!!!!!!!', on
Thu, 1 Jan 2004:

>Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
>and levers! 

But I bet you enjoyed the tutorials with Lady Ada!
-- 
Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk 
Interested in professional sound reinforcement and distribution? Then go to 
http://www.isce.org.uk
PLEASE do NOT copy news posts to me by E-MAIL!

Article: 64406
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: DJ <Garbage.davidjudy@optusnet.com.au>
Date: Fri, 02 Jan 2004 17:26:25 +1100
Links: << >>  << T >>  << A >>
On Fri, 2 Jan 2004 05:36:35 +0000, John Woodgate <jmw@jmwa.demon.contraspam.yuk>
wrote:

>I read in sci.electronics.design that Bob Perlman
><bobsrefusebin@hotmail.com> wrote (in <9d99vv0o606si8gvj10cgrsu35k1n011c
>4@4ax.com>) about 'SOS : 4-bit binary divider circuit PLEASE!!!!!!!', on
>Thu, 1 Jan 2004:
>
>>Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
>>and levers! 
>
>But I bet you enjoyed the tutorials with Lady Ada!

An analytical deduction?

Article: 64407
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: DJ <Garbage.davidjudy@optusnet.com.au>
Date: Fri, 02 Jan 2004 17:29:46 +1100
Links: << >>  << T >>  << A >>
On Thu, 01 Jan 2004 22:53:26 GMT, Bob Perlman <bobsrefusebin@hotmail.com> wrote:

>On Thu, 1 Jan 2004 17:17:38 -0500, "Jerry" <nospam@nowhere.com> wrote:
>
>>WOW, your prof let you use NANDs? we had to do this using only
>>relays. Wish I had an easy prof like yours.
>>
>>(:>)
>>
>>Jer
>
>Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
>and levers!  Compared to that experience, designing with today's EDA
>tools seems...well, pretty much the same, actually.
>
>Bob Perlman
>Cambrian Design Works
>

Based on the OP's email address, the thing should be implemented using only
Aristotelian propositions.

dj

Article: 64408
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: wouter@voti.nl (Wouter van Ooijen (www.voti.nl))
Date: Fri, 02 Jan 2004 06:55:32 GMT
Links: << >>  << T >>  << A >>
>If I were your prof, and I caught you blatantly trying to get others to do your
>thinking for you, I'd make you design it using nothing but BC547's, resistors
>and diodes. That way you might l-e-a-r-n something. That is why you are at uni?

Why would he need diodes?



Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
PICmicro chips, programmers, consulting

Article: 64409
Subject: Virtex2Pro + SysGen
From: "Terrence Mak" <stmak@se.cuhk.edu.hk>
Date: Fri, 2 Jan 2004 15:34:39 +0800
Links: << >>  << T >>  << A >>
Hi,
How to embedded the powerpc as a submodule in the sysgen environment?
I have tried to export the hdl files from XPS, then use the blackbox block
provided from SysGen, but, cannot go through the ISE synthesis.
Any idea to acheive this?

Terrence



Article: 64410
Subject: help for Viterbi decoder design
From: inaganti_suni@yahoo.com (sunil)
Date: 2 Jan 2004 00:57:37 -0800
Links: << >>  << T >>  << A >>
hello,
          i am doing project on implementing viterbi decoder on FPGA.
i know theory about Viterbi decoding. i dont know anything about FPGA.
can body can help regarding this by telling how i can approach for
that.
     thanking you.

Article: 64411
Subject: Partitioning Problem in FPGA and Its Embedded PC Core
From: fac_4u@hotmail.com (Farhan)
Date: 2 Jan 2004 04:18:46 -0800
Links: << >>  << T >>  << A >>
Hi! 

I am currently working on scheduling / partitioning algorithms for
Multi-Level Task handling using Xilinx Vertex II Pro. Do anybody know
if some work have been done on partitioning algorithms for assignment
of tasks to Embedded Microprocessor (embedded in FPGA - Xilinx Vertex
II Pro) and FPGA it self.

Farhan A Chughtai 
Undergrad. 
University of Engineering and Technology,Lahore

Article: 64412
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: bill.sloman@ieee.org (Bill Sloman)
Date: 2 Jan 2004 05:01:09 -0800
Links: << >>  << T >>  << A >>
DJ <Garbage.davidjudy@optusnet.com.au> wrote in message news:<1o3avv4gkghgrkpg47uej6hdaaqr7f55rc@4ax.com>...
> On Fri, 2 Jan 2004 05:36:35 +0000, John Woodgate <jmw@jmwa.demon.contraspam.yuk>
> wrote:
> 
> >I read in sci.electronics.design that Bob Perlman
> ><bobsrefusebin@hotmail.com> wrote (in <9d99vv0o606si8gvj10cgrsu35k1n011c
> >4@4ax.com>) about 'SOS : 4-bit binary divider circuit PLEASE!!!!!!!', on
> >Thu, 1 Jan 2004:
> >
> >>Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
> >>and levers! 
> >
> >But I bet you enjoyed the tutorials with Lady Ada!
> 
> An analytical deduction?

You didn't want to bet with Lady Ada - she had one of those betting
schemes that had made many bookmakers rich. Betting against her didn't
work any better.

------
Bill Sloman, Nijmegen

Article: 64413
Subject: Re: Reverse engineering an EDIF file?
From: Joonas Timo Taavetti Kekoni <jkekoni@cc.hut.fi>
Date: Fri, 2 Jan 2004 15:57:52 +0200 (EET)
Links: << >>  << T >>  << A >>
In comp.lang.vhdl Jim Lewis <Jim@synthworks.com> wrote:
: You would be better off working with a good legal agreement
: and people who you can trust to abide by it.

One does not really make an agreement over a deadline.
It is just sometimes easier to uncompile things, providing this
is possible. (If you are talking only about bying a licence,
this should be quick providing you can arrange the money quickly.)

I have been working over a project that the technical person
claims that the bug does not exists or it was fixed a long time ago,
(do not remember anymore which one ) despite we had showed wery clearly 
that the big is there. (In reality the bug has been fixed on a subsequent,
but incompatible release of the program, which was not compatible
with out software at that time.)

We send the uncompiled file to that person, with exlanation what happens,
when why. ... The fix got into the next sevice release. 

We were not major client, they would most likely been more
likely to lose us, that to give out sourcecode to debug a bug
"which is not there".




Article: 64414
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: Jim Thompson <invalid@invalid.invalid>
Date: Fri, 02 Jan 2004 07:10:19 -0700
Links: << >>  << T >>  << A >>
On Fri, 02 Jan 2004 06:55:32 GMT, wouter@voti.nl (Wouter van Ooijen
(www.voti.nl)) wrote:

>>If I were your prof, and I caught you blatantly trying to get others to do your
>>thinking for you, I'd make you design it using nothing but BC547's, resistors
>>and diodes. That way you might l-e-a-r-n something. That is why you are at uni?
>
>Why would he need diodes?
>
>Wouter van Ooijen
>

No diodes needed, just RTL structures ;-)

                                        ...Jim Thompson
-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Article: 64415
Subject: Re: Net name convention for Xilinx UCF files.
From: PO Laprise <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca>
Date: Fri, 02 Jan 2004 17:33:46 GMT
Links: << >>  << T >>  << A >>
One Day & A Knight wrote:

> I do remember there is a document said all the names and definitions in the
> source code will
> remain unchanged, but how come it doesn't in my case.
> 
> In the source code, there is no simple *u_testctrl?clk36_pll_o. All I found
> from the ngd2ver is a
> totally new definition u_testctrl/Mmux_clk36_pll_o_Result1_1. This is quite
> strange to me.

In my experience, the synthesis tools do a relatively good job of 
keeping the net names, or something very close, but sometimes it just 
isn't possible.  Often, some nets are duplicates of other nets, 
optimized out, merged, or G knows what else...  Try to follow the 
netlist logic to see whether this is truly the net that you want (you 
should be able to tell by examining the other nets that join it to form 
logic functions).  Personally, I use X's constraints editor initially to 
find the net, and then edit my UCF manually or with scripts.  The 
synthesis tools rarely cause me problems by spuriously changing net 
names on me on subsequent syntheses barring major changes in my code.

-- 
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --


Article: 64416
Subject: Re: help for Viterbi decoder design
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 2 Jan 2004 10:23:54 -0800
Links: << >>  << T >>  << A >>
inaganti_suni@yahoo.com (sunil) wrote in message news:<9f28d282.0401020057.5a933dad@posting.google.com>...
> hello,
>           i am doing project on implementing viterbi decoder on FPGA.
> i know theory about Viterbi decoding. i dont know anything about FPGA.
> can body can help regarding this by telling how i can approach for
> that.
>      thanking you.


Well, first off all, I would suggest that you "just start"
writing the decoder. Do it the best way you know how to. And
than see where you get stuck. There is nothing special about
FPGAs (unless you want to use some special functionalities
like DPLL for example).

Once you make some sort of an effort and can show people
where you are stuck, you will get lots of help and support
from other designers.

Also visit www.opencoreas.org, and join the cores mailing
list. Once you have made an effort and can demonstrate the
problem you are having, I'm sure many people will be happy
to help you !

Good Luck !

Best Regards,
rudi
========================================================
   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Article: 64417
Subject: Newbie Question: Compiling VHDL in Mentor Graphics
From: "jk" <z3015094NOSPAM@student.unsw.edu.au>
Date: Sat, 3 Jan 2004 19:03:21 +1100
Links: << >>  << T >>  << A >>
Hi all,

trying to get my head around mentor graphics. I have typed a bunch of code
and I am now trying to compile it. I am using Mentor Graphics.

Basically I go into the HDL designer window, set a root for my design and I
then click on the task manager icon which brings up a list of tasks for me
to carry out on the VHDL code. I click on 'Generate' which responds by
indicating 'Generation Completed Succesfully'. I then set the ModelSim
compile path to the following:


'D:\HDL\HDS_PROJECTS\ADAPTIVE_ENCODER_TRANSMITTER\ADAPTIVE_ENCODER_TRANSMITT
ER_LIB\HDL'

In that the above directory holds my vhdl files. I then click ModelSim
compile and I get the following response, which it pauses on:

Performing compile...
Library adaptive_encoder_transmitter_lib
executing
D:/HDL/HDS_PROJECTS/ADAPTIVE_ENCODER_TRANSMITTER/ADAPTIVE_ENCODER_TRANSMITTE
R_LIB/HDL/vlib
D:/HDL/hds_projects/adaptive_encoder_transmitter/adaptive_encoder_transmitte
r_lib/work

Like I mentioned...this is as far as it goes. Looking at my CPU processes,
it doesn't actually seem to be doing anything.

Any ideas? Or is there some other way to get my vhdl files to compile? I am
using HDL Designer 2003.2.

cheers

- Kingsley



Article: 64418
Subject: Re: Question on partial reconfiguration flow...Must use EDIF flow?
From: "A Day & A Knight" <kelvin8157@hotmail.com>
Date: Sat, 3 Jan 2004 23:01:40 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I managed to use NGC file to replace NGO and a single ISE6.1 Webpack can do
a partial reconfiguration now. Thank you for your postings.

Best Regards,
Kelvin







"A Day & A Knight" <kelvin8157@hotmail.com> wrote in message
news:bt0mud$6mb$1@mawar.singnet.com.sg...
> Hi, there:
>
> I am a little confused with the partial reconfiguration flow.
>
> In the Active module implementation, I found that I must use the *.NGO
file.
> However .NGO file is only
> available when I use EDIF file as input, and XST cannot produce EDIF file.
>
> Does it mean I have no choice but to use something other than XST (e.g.
> Synplicity) to synthesize my designs?
>
> ngdbuild  -p xc2v250-fg256-4 -modular module -active iq_gen
> ../../top1/initial/sig_gen.ngo
>
> Best Regards,
> Kelvin
>
>
>
>



Article: 64419
Subject: please help! state machine
From: "Simone Winkler" <simone.winkler@gmx.at>
Date: Sat, 3 Jan 2004 19:38:14 +0100
Links: << >>  << T >>  << A >>
Hello!

I've got a strange problem that I don't know any solution for - up to now I
tried everything, but it didn't work.
The state machine always stops to go to the next state - I
really don't understand why.

I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains in
the WRITE_INIT state all the time. WHY????
The 2nd (smaller) problem is, that the data at write_out comes one clock
cycle too late. I understand why, but how can i change this?

I don't know if it's a good idea to solve my problem with my kind of code,
i'm an "advanced beginner" and as I am used to program "sequential
programming languages" I've got big problems with doing sequential things in
vhdl. What is the easy way to do things one after the other, e.g. write one
byte after the other? (also to be synthesizable).

I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because it's
quite long to put it here. (don't be afraid - no virus!)

Please help me! I really don't know where to go on.

Thank you,
Simone



Article: 64420
Subject: Response to ALuPin@web.de on high level simulation
From: joe@hal.com (joe)
Date: Sat, 3 Jan 2004 22:47:52 +0000 (UTC)
Links: << >>  << T >>  << A >>
Andre,  You posted an article saying you want to simulate your design but you 
have components that can not be easily reproduced by models.  Give 
SeaHDL/SimHDL a try at http://etherdesign.tripod.com.  It was originally 
intended for people doing radio DSP.  The design is done is a "C-like" code 
with VERILOG extensions.  It then outputs a VERILOG file and a schematic.  The 
schematic is imported to a simulator which can simulate RF signals, noise, 
multipath, etc.  It lets you see the design in a hierarchical format, browze 
and plot out any nodes in the design. 


Article: 64421
Subject: C-NIT based complete SoC + FPGAProto preview
From: do_not_reply_to_this_addr@yahoo.com (Sumit Gupta)
Date: 3 Jan 2004 16:18:31 -0800
Links: << >>  << T >>  << A >>
Hi

I have updated http://www.c-nit.net with a complete SoC system
including processor, SDRAM controller, cache controller, keyboard
controller and some glue logic. Also ported the sasm assember to
windows as a win32 console app.

Along with this I also put in a preview of the FPGAProto board I
built.

Thanks
Sumit Gupta

http://www.c-nit.net

Article: 64422
Subject: Re: please help! state machine
From: "rAinStorms" <chris_karma@xtra.co.nz>
Date: Sun, 4 Jan 2004 15:11:39 +1300
Links: << >>  << T >>  << A >>
What program you using ..Quartus?

"Simone Winkler" <simone.winkler@gmx.at> wrote in message
news:1073153426.69428@news.liwest.at...
> Hello!
>
> I've got a strange problem that I don't know any solution for - up to now
I
> tried everything, but it didn't work.
> The state machine always stops to go to the next state - I
> really don't understand why.
>
> I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
> VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains
in
> the WRITE_INIT state all the time. WHY????
> The 2nd (smaller) problem is, that the data at write_out comes one clock
> cycle too late. I understand why, but how can i change this?
>
> I don't know if it's a good idea to solve my problem with my kind of code,
> i'm an "advanced beginner" and as I am used to program "sequential
> programming languages" I've got big problems with doing sequential things
in
> vhdl. What is the easy way to do things one after the other, e.g. write
one
> byte after the other? (also to be synthesizable).
>
> I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because
it's
> quite long to put it here. (don't be afraid - no virus!)
>
> Please help me! I really don't know where to go on.
>
> Thank you,
> Simone
>
>



Article: 64423
Subject: HDL Bencher question
From: Jon Elson <elson@pico-systems.com>
Date: Sat, 03 Jan 2004 20:15:45 -0600
Links: << >>  << T >>  << A >>
Hello,

I'm trying to set up a simulation testbench using the HDL Bencher
in ise 4.2i (I have to use that old software, as I am using 5 V
original Spartan chips).  It seems that bidirectional buses
can be checked for results, but can't be forced!  It displays
with yellow background (inactive) and I've found no way to drive
the bus from the testbench (make it go to blue background or active).

What am I missing here?  The manual, even an additional one I downloaded
from the Xilinx web site, was pretty sketchy.  Otherwise, it is a really
nice tool for setting up a testbench.

Thanks in advance for any pointers on this.

Jon


Article: 64424
Subject: Complicated clocking in an FPGA.
From: "A Day & A Knight" <kelvin8157@hotmail.com>
Date: Sun, 4 Jan 2004 10:22:09 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I have ASIC source codes from a previous communication chip. It has some 23
clocks,
many of them are derived from a 144MHz clock (72/36/24/18/.../2/1MHz), only
three from
other sources. The ASIC codes made use of a clock generator with clock
gating...

How am I going to handle all these different clocks? In a Vertex chip, there
is only 16 clock buffers.

May I use a "always @ posedge clk144mhz clk72mhz <= ~clk72mhz " to generate
a 72mhz while
use same global buffer as 144mhz?

Best Regards,
Kelvin






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Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMar2019

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