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Messages from 64650

Article: 64650
Subject: Re: Large/Fast static RAM
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Sat, 10 Jan 2004 08:05:39 GMT
Links: << >>  << T >>  << A >>
John,

RLDRAM looks very interesting.  A quick price and availability in the Avnet
site does not show these parts as being readily available.  Nothing like the
bleeding edge!  Maybe a phonecall or two is required.  I also saw the Memec
P160 demo module.  I have the Memec V2 Microblaze board that takes these
P160's, so it would be very easy to evaluate the solution.

Thanks,


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"





"john jakson" <johnjakson@yahoo.com> wrote in message
news:adb3971c.0401091904.8a294ef@posting.google.com...
> "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:<lEgLb.1476$rt.397@newssvr29.news.prodigy.com>...
> > I'm trying to determine if anyone makes a large/fast static RAM part.
16M
> > (or more) x 16 bits (or more), 10ns.
> >
> > I can't afford the address-to-data-out latency of dynamic RAM.  There
are
> > ways around this, of course, but SRAM would be so much simpler.
> >
> > Any ideas?
> >
> > Thanks,
>
> As everyone has said, SRAM is not an option at 16.16M for many many
> years.
>
> Ordinarily DRAM isn't an option either at 10ns atleast not SDRAM &
> DDRAM.
>
> But if you can live with 20ns RAS cycle RLDRAM can do it, at 256M
> today. Its 8 way banked and has separate IO for brutal bandwidth at
> 400MHz by 8,16,32. look at Infineon and Micron sites.
>
> Xilinx has docs on it as well in their memory section. Avnet IIRC has
> an eval board with a slightly slower version.
>
> There are also other faster DRAMs from the other guys, but not quite
> as fast as I can tell.
>
> IBM makes DRAM that cycles in 5ns or so for internal cache (EET
> article), but I don't think there will be any external product at that
> speed till the DRAM guys get demand from...
>
> Hope that helps
>
> johnjaksonATusaDOTcom



Article: 64651
Subject: ISE6.1 rom16X1 initialization INIT
From: "Keith R. Bolson" <krbolson@visi.com>
Date: Sat, 10 Jan 2004 02:18:58 -0600
Links: << >>  << T >>  << A >>
Hello all -

   I used the source rom.vhd at the bottom of:
http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm
under Webpack ISE6.1 VHDL and was surprised that XST bombs on synthesis.
  FATAL_ERROR:Xst:Portability/export/Port_Main.h:127.1.13 -
  This application has discovered an exceptional condition from which it
  can not recover.  Process will terminate.  ...

So I tried it in webpack ISE5.1; it synthesized and simulates fine.
I tried re-installing ISE6.1 and related service packs, no change.
   What am I missing?



Article: 64652
Subject: Re: Xilinx ECS - connecting a single net to multiple bus lines?
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 10 Jan 2004 09:53:18 GMT
Links: << >>  << T >>  << A >>
On Wed, 07 Jan 2004 21:36:15 -0000, ad.rast.7@nwnotlink.NOSPAM.com (Alex Rast) wrote:

A)
>What's the way to do this? It's common for me to run into situations where 
>I have a bus or bus pin, and I need to connect the same net to different 
>lines on the bus.

B)
>Another common one is I have 2 busses, both of which have 
>a line that should connect to a single net. The documentation doesn't seem 
>to give any hints. Thanks for any input.

While I have not used ECS, the way we did this in previous schematic
systems was to pass the source single through multiple "BUF" symbols.

Look in the libraries guide:

   http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm

      Libraries Guide -> Design Elements -> BUF

A) sourcenet -> BUF -> dest_bus_[2]
   sourcenet -> BUF -> dest_bus_[3]

B) SourceBusBit_[3] -> BUF -> DestBusBit_[6]

The BUF is a primitive that uses no logic resources. It is used to alias
one signal name to another, and is trimmed out during the P&R process


Philip



===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

Article: 64653
Subject: Re: old articels of this newsgroup
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 10 Jan 2004 02:04:06 -0800
Links: << >>  << T >>  << A >>
On Thu, 08 Jan 2004 09:32:00 +0100, Tobias Möglich <Tobias.Moeglich@gmx.net> wrote:
>Hello.
>
>Does anyone no where to find the older (Sept-Dez 2003) articles of this
>newsgroup ???
>
>Greetings Tobias

All articles for comp.arch.fpga are archived at 

    http://www.fpga-faq.com/archives/index.html




===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

Article: 64654
Subject: Re: FPGA Size
From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
Date: Sat, 10 Jan 2004 12:06:14 +0200
Links: << >>  << T >>  << A >>
Fitter (place&route) will tell you. Report looks like:

Macrocells     Product Terms    Registers      Pins           Function Block
Used           Used             Used           Used           Inputs Used
39 /72  ( 54%) 337 /360  ( 94%) 38 /72  ( 53%) 4  /34  ( 12%) 140/216 ( 65%)



Article: 64655
Subject: Re: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 10 Jan 2004 10:18:42 GMT
Links: << >>  << T >>  << A >>
On Thu, 8 Jan 2004 23:44:16 +0800, "Kelvin @ SG" <kelvin8157@hotmail.com> wrote:
>Thanks for any response...I fixed this error with "// synthesis attribute
>INIT of lut_gnd is 00" to replace defparameter.
>
>However, I don't understand why this INIT used a "8000"? How do I derive
>this 8000?
>
>Best Regards,
>Kelvin
>
>Verilog Syntax:
>
>module top (O, I0, I1, I2, I3);
>input I0, I1, I2, I3;
>output O;
>
>LUT4 U1 (.O(O), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
>// synthesis attribute INIT of U1 is "8000"
>endmodule

The LUT is a 16 bit memory. The "8000" is a 16 bit constant.

The 8000 is the initialization value for the 16 bit memory,

The MSB (the bit that makes it 8000 not 0000) of the memory
is addressed by I0, I1, I2, I3 having the value 1,1,1,1

I.E. this constant implements a 4 input AND gate.

The value FFFE implements a 4 input OR gate

There are 65536 possible init values, many are interesting.

    http://www.fpga-faq.com/archives/23500.html#23505




===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

Article: 64656
Subject: Re: ISE6.1 rom16X1 initialization INIT
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 10 Jan 2004 10:39:02 GMT
Links: << >>  << T >>  << A >>
On Sat, 10 Jan 2004 02:18:58 -0600, "Keith R. Bolson" <krbolson@visi.com> wrote:
>Hello all -
>
>   I used the source rom.vhd at the bottom of:
>http://www.fpga-faq.com/FAQ_Pages/0031_How_to_initialize_Block_RAM.htm
>under Webpack ISE6.1 VHDL and was surprised that XST bombs on synthesis.
>  FATAL_ERROR:Xst:Portability/export/Port_Main.h:127.1.13 -
>  This application has discovered an exceptional condition from which it
>  can not recover.  Process will terminate.  ...
>
>So I tried it in webpack ISE5.1; it synthesized and simulates fine.
>I tried re-installing ISE6.1 and related service packs, no change.
>   What am I missing?
>

If it works in 5.1 and crashes in 6.1 then it looks like a bug.

You are not "missing" anything. Report it to Xilinx with your test case.

Philip




===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM

Article: 64657
Subject: Re: Spartan3 IOB without supply
From: news@sulimma.de (Kolja Sulimma)
Date: 10 Jan 2004 03:36:04 -0800
Links: << >>  << T >>  << A >>
In this particular board VCCIO is connected to 2.5V or 3.3V depending
on what mezzanine board is connected.
Now I want to use the existing board without a mezzanine board. 
Of course I can solder shorts on the connector. But thats ugly.
Decoupling caps are there, so at least a high frequency return path is
available.

For a later revision of the board: 
2mA could be provided by a 1k resistor to 3.3V. And I still could
connect 2.5V (at a standby power penalty).
Or would the impedance of the return path be to large in that case?

Question 2:
I thought I read somewhere that the for LVDS standard the IO drivers
are powered by VCCAUX. But looking at the datasheet again this does
not seem to be the case.

Thank you for your help,

Kolja Sulimma

Austin Lesea <austin@xilinx.com> wrote in message news:<btmis4$1vo1@cliff.xsj.xilinx.com>...
> Kolja,
> 
> Not recommended.  If nothing is used, the current consumed is ~ 2mA per 
> bank, so why do you want to leave them disconnected?  You do not have to 
> provide bypass caps if they are not used, so there is little penalty. 
> Conencting it up provides the return paths for the ESD protection, etc.
> 
> Per question 2:  I do not understand.  Vccaux is 2.5V, so only 2.5V LVDS 
>   IOB primitive is supported.  Since LVDS is a standard, 2.5V or 3.3V 
> makes no difference at all:  a 2.5V powered LVDS buffer receives or 
> drives a 3.3V LVDS buffer.
> 
> And finally, no, you must connect Vcco is you are to use the IOB at all, 
> for any reason.
> 
> Austin
> 
> Kolja Sulimma wrote:
> 
> > Austin, 
> > 
> > you are probably the right person to answer these questions about
> > Spartan-3:
> > 
> > 1.
> > If I use no IOBs of a given Bank at all, can I leave VCCIO of that
> > bank unconnected?
> > 
> > 2.
> > Can I still use VCCAUX based IO standards like LVDS?
> > 
> > 3. 
> > Can I use open collector like outputs without VCCIO connected?
> > (Eg conditionally pull an output to ground)
> > 
> > This request might sound strange, but we have a board where VCCIO of
> > two banks is supplied by another board. No a new application was
> > brought up were the second board is not needed except for the
> > generation of VCCIO. SO I would like to get rid of it.
> > 
> > Thank you in advance,
> > 
> > Kolja Sulimma

Article: 64658
Subject: What is wrong with my DCM experiment? How come the testbench won't simulate DCM1.
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Sat, 10 Jan 2004 22:36:27 +0800
Links: << >>  << T >>  << A >>
Hi, there:

What is wrong with my DCM experiment? How come the testbench won't simulate
DCM1, the clk1 is low.
DCM0 is working fine though.

Thanks.
Kelvin



`include "D:/dsp/src/defines.v"


module dcm_clkman(
 clock_in,
 clock_2_out,
 clock_3_out,
 clock_with_ps_out,
 reset
);
input clock_in;
output clock_2_out;
output clock_3_out;
output clock_with_ps_out;
output reset;

wire low;
wire high;
wire dcm0_locked;
wire dcm1_locked;
wire reset;
wire clk0;
wire clk1;
assign low = 1'b0;
assign high = 1'b1;
assign reset = ~ (dcm0_locked & dcm1_locked);

wire clock_2_out;
wire clock_3_out;

assign clock_2_out = clk0;
assign clock_3_out = clk1;

IBUFG CLOCK_IN (
 .I(clock_in),
 .O(clock)
);

DCM DCM0 (
 .CLKFB(clock_out),
 .CLKIN(clock),
 .DSSEN(low), .PSCLK(low), .PSEN(low), .PSINCDEC(low), .RST(low),
 .CLK0(), .CLK90(),  .CLK180(), .CLK270(),
 .CLK2X(clk0),  .CLK2X180(),
 .CLKDV(),
 .CLKFX(),  .CLKFX180(),
 .LOCKED(dcm0_locked),   .PSDONE(), .STATUS()
);
/* synthesis xc_props="DLL_FREQUENCY_MODE = LOW,DUTY_CYCLE_CORRECTION =
 TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE =
 1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT =
 NONE,PHASE_SHIFT = 0" */
// Do not insert any carriage return between the
// lines above.
BUFG CLK_BUF0(
 .O(clock_out),
 .I(clk0)
);

DCM DCM1 (
 .CLKFB(clock_with_ps_out),
// .CLKFB(),
 .CLKIN(clock),
 .DSSEN(low), .PSCLK(low), .PSEN(low), .PSINCDEC(low), .RST(low),
 .CLK0(),  .CLK90(),  .CLK180(), .CLK270(),
 .CLK2X(),  .CLK2X180(),
 .CLKDV(),
 .CLKFX(clk1),  .CLKFX180(),
 .LOCKED(dcm1_locked),   .PSDONE(), .STATUS()
);

/*synthesis xc_props="DLL_FREQUENCY_MODE =LOW,DUTY_CYCLE_CORRECTION =
TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE =
1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT =
FIXED,PHASE_SHIFT = 0" */
//Do not insert any carriage return between the
//lines above.
BUFG CLK_BUF1(
 .O(clock_with_ps_out),
 .I(clk1)
);
//The following Verilog code is for simulation only
//synthesis translate_off
defparam DCM0.DLL_FREQUENCY_MODE = "LOW";
defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM0.STARTUP_WAIT = "TRUE";
defparam DCM0.DFS_FREQUENCY_MODE = "LOW";
defparam DCM0.CLKFX_DIVIDE = 1;
defparam DCM0.CLKFX_MULTIPLY = 2;
defparam DCM0.CLK_FEEDBACK = "1X";
defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM0.PHASE_SHIFT = 0;

defparam DCM1.DLL_FREQUENCY_MODE = "LOW";
defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM1.STARTUP_WAIT = "TRUE";
defparam DCM1.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM1.DFS_FREQUENCY_MODE = "LOW";
defparam DCM1.CLKFX_DIVIDE = 2;
defparam DCM1.CLKFX_MULTIPLY = 3;
defparam DCM1.CLK_FEEDBACK = "1X";
defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED";
defparam DCM1.PHASE_SHIFT = 0;
//synthesis translate_on
endmodule // DCM_TOP



Article: 64659
Subject: Dedicated CLK lines in CPLD
From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
Date: Sat, 10 Jan 2004 21:13:36 +0200
Links: << >>  << T >>  << A >>
I divide primaty CLK1 signal from chip input getting CLK2. CLK2 is submitted
to the remaining design. This should consume 2 GCLK (XC9572 CPLD) lines.
However fitter tells me that only 1 of 3 3 GCLK lines used. Design seems to
function properly. ChipViewer does not want to show me chip internals.



Article: 64660
Subject: clarity on Gibson Guitar Story(ies)
From: tim colleran <tcollera@pacbell.net>
Date: Sat, 10 Jan 2004 19:36:13 GMT
Links: << >>  << T >>  << A >>


Perhaps I can shed a bit of light on the Altera piece of this story. I 
think our press release states things pretty clearly, but evidently has 
been misinterpreted a bit.

Altera won a design with Cyclone and NIOS in a module that allows a 
variety of different instruments to connect into Gibson's innovative 
MaGIC digital music technology. In doing so, Cyclone replaced a 
competitive FPGA and a small processor. This is not in the guitar but in 
the technology that enables Gibson to reach a much broader audience with 
MaGIC. Hence the headline that we are helping Gibson to Spread MaGIC.

It appears as though since the name of the company is Gibson Guitar, 
many people automatically assumed the release was about the actual 
guitar without reading the details.

As for why Gibson chose Altera, as I understand it there were both 
technical and business reasons behind their decision. The combination of 
NIOS and Cyclone fit the application well. I also believe that Gibson 
sees the benefits of a two vendor model.

On the guitar side of things, I don't have any reason to doubt that 
Gibson intends to use Xilinx in production for the Guitar. While I could 
speculate further, it would be innappropriate and unprofessional.

Hopefully that sheds some light on what Altera announced. Any confusion 
on the topic was purely unintentional.

Tim Colleran
Altera Corporation






Ralph Malph wrote:
> Hal Murray wrote:
> 
>>>The downside is that to do this you have to make your HDL code generic,
>>>not using any of the special features of either family of parts.  This
>>>allows you to reuse the code in the next design without a lot of porting
>>>troubles.
>>
>>Plan 1 is that you write your code so it runs on several vendors,
>>and then you play them against eachother for a low price.
>>
>>Plan 2 would be to write your code to take advantage of a the
>>features on a specific vendor (and part) so you get denser/faster
>>results, maybe working in a smaller or slower and hence cheaper
>>part.
>>
>>Anybody have estimates of how much each approach would save?  Or
>>how much manpower each approch takes?  The first approach might
>>be better if you have a good purchasing dept that likes playing
>>that type of game - offload some of the work to somebody else.
> 
> 
> The second approach only works if you use your code in a single design. 
> Most designers code for reuse since they often work on multiple projects
> with similar functions.  In our case, they had many products that used
> the same designs, often with additions.  So if the original unit used a
> chip from X and the next generation used a chip from A, they did not
> want to have to recode the optimizations.  On the other hand, they often
> did have to code for the given chip when they added features to fielded
> units and needed to push the capacity.


Article: 64661
Subject: Re: Anybody know what the REAL story is? Jim figured it out.
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Sat, 10 Jan 2004 12:17:27 -0800
Links: << >>  << T >>  << A >>
Hal Murray wrote:
>>The downside is that to do this you have to make your HDL code generic,
>>not using any of the special features of either family of parts.  This
>>allows you to reuse the code in the next design without a lot of porting
>>troubles.
> 
> 
> Plan 1 is that you write your code so it runs on several vendors,
> and then you play them against eachother for a low price.
> 
> Plan 2 would be to write your code to take advantage of a the
> features on a specific vendor (and part) so you get denser/faster
> results, maybe working in a smaller or slower and hence cheaper
> part.
> 
> Anybody have estimates of how much each approach would save?  Or
> how much manpower each approch takes?  The first approach might
> be better if you have a good purchasing dept that likes playing
> that type of game - offload some of the work to somebody else.


The architectures for A and X are so close in the latest
devices that there are few device primitives that cannot
be inferred by synthesis using generic code. So I would
use Plan 1 for new designs just for code clarity and
ease of simulation. The only reason I might even consider
using Plan 2 might be to reuse working code.

In a large company, engineers might best leave final price
negotiations to purchasing. In a small company, it is more
important to establish a good relationship with an fpga
distributor than it is to play price games. The distributor
is in the best position to get you proto samples of that
new part that isn't quite available yet.

      -- Mike Treseler


Article: 64662
Subject: Re: Dedicated CLK lines in CPLD
From: "tbx135" <tbx135@msn.com>
Date: Sat, 10 Jan 2004 20:23:46 GMT
Links: << >>  << T >>  << A >>
> I divide primaty CLK1 signal from chip input getting CLK2. CLK2 is
submitted
> to the remaining design. This should consume 2 GCLK (XC9572 CPLD) lines.
> However fitter tells me that only 1 of 3 3 GCLK lines used. Design seems
to
> function properly. ChipViewer does not want to show me chip internals.

If CLK1 is connected to the GCK line and drives the FF used in the divider.
CLK2 is the output of the FF and is sent through-out the device as a product
term clock. This is not a good design practice as routing resources
introduce skew, even in CPLD's. CLK2 needs to be assigned to an internal GCK
resource by instantiating the global clock component.



Article: 64663
Subject: Re: Dedicated CLK lines in CPLD
From: "Karl Olsen" <karl.olsen@mail.dk>
Date: Sat, 10 Jan 2004 22:02:31 +0100
Links: << >>  << T >>  << A >>
valentin tihomirov <valentin_NOSPAM_NOWORMS@abelectron.com> wrote:

> I divide primaty CLK1 signal from chip input getting CLK2. CLK2 is
> submitted to the remaining design. This should consume 2 GCLK (XC9572
> CPLD) lines. However fitter tells me that only 1 of 3 3 GCLK lines
> used. Design seems to function properly. ChipViewer does not want to
> show me chip internals.

You can check the chip internals in the fitter report file (.rpt).

The only way to use the global clock nets is by inputting the clock on a GCK
pin.  If using product term clocks, as you do now, consumes too may product
terms, you can output the divided clock on an output pin, and then
externally wire it to another GCK pin.  If you aren't short of product
terms, you can just leave it as it is.

It is also possible to output the divided clock on a GCK pin, and then using
the same pin as the divided GCK input, wasting only one pin for this.  The
fitter is very keen on "optimizing" this arrangement away, so you need to
tell it using attributes, that you really want the clock signal taken from
the pin (and using the global clock net), and not from the internal signal
that you output on it.

Karl Olsen



Article: 64664
Subject: Altera Cyclone Serial Configuration devices.
From: Rene Tschaggelar <none@none.none>
Date: Sat, 10 Jan 2004 21:36:05 GMT
Links: << >>  << T >>  << A >>
I started reading some documents about the configuration
devices EPCS1 & EPCS4. They appear to be programmed with a
new download cable, the Byteblaster2.
The Byteblaster2 claims compatibility with the previous models,
the Byteblaster and the ByteblasterMV. Unfortunately, there
is no schematics included in the Byteblaster2 datasheet.
Is the 74HC244 being changed to a 74LV244 this time ?


Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 64665
Subject: Spartan-3 LC Development Kit from Insight (Memec)
From: remis norvilis <norvilis@charter.net>
Date: Sat, 10 Jan 2004 15:38:48 -0600
Links: << >>  << T >>  << A >>
I'm considering to get Spartan-3 LC Dev. Kit (DS-KIT-3SLC400) from Insight.
Anybody used it? Comments would be appreciated.

Remis

Article: 64666
Subject: Programming and debugging the Altera Cyclone family
From: Rene Tschaggelar <none@none.none>
Date: Sat, 10 Jan 2004 22:04:32 GMT
Links: << >>  << T >>  << A >>
According to the Serial Configuation Devices() Datasheet
(chapter 4 of configuration handbook volume 2),
I understand that the Cyclones and their configuration devices
are programmed in the so called AS  mode with the Byteblaster2.

Debugging is done with the usual JTAG connector, I assume.
The Byteblaster2 also supports JTAG.

Meaning I have to swap the connector ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 64667
Subject: Re: Altera Cyclone Serial Configuration devices.
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Sat, 10 Jan 2004 14:50:37 -0800
Links: << >>  << T >>  << A >>
Rene Tschaggelar wrote:
> I started reading some documents about the configuration
> devices EPCS1 & EPCS4. They appear to be programmed with a
> new download cable, the Byteblaster2.
> The Byteblaster2 claims compatibility with the previous models,
> the Byteblaster and the ByteblasterMV. Unfortunately, there
> is no schematics included in the Byteblaster2 datasheet.
> Is the 74HC244 being changed to a 74LV244 this time ?

Byteblaster2 is a superset of MV -- more than a buffer.
But I expect that the MV can program an EPCS1.

           -- Mike Treseler


Article: 64668
Subject: Re: FLASH memory programming with Altera NIOS and same question for Xilinx
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 11 Jan 2004 00:36:26 +0100
Links: << >>  << T >>  << A >>
george.martin@att.net (George) writes:

> I think you mean "rom" is housed in the fpga.  Perhaps a small boot
> program would fit into the the FPGA rom space.  But I'm afraid a full
> fpga would not have enough space.  I'll look into that and post a
> follow up message here.  Any ohter suggestions.

Altera has a boot monitor program called GERMS. You can upload a FPGA
configuration with GERMS in on-board ROM. You can then use nios-run to
upload and run code NIOS code, which again could read data from some
other interface and upload the FPGA configuration to the FLASH (as
others have suggested).

If you plan on a production run (and test) I would suggest looking
into programming the FLASH using the JTAG port of the FPGA. JTAG
Technologies (and others) have software for this:

(http://www.jtag.com/index.php?lg=en&p=3210)

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 64669
Subject: Re: Altera Cyclone Serial Configuration devices.
From: "Simon Peacock" <nowhere@to.be.found>
Date: Sun, 11 Jan 2004 16:46:45 +1300
Links: << >>  << T >>  << A >>
I believe there's an extra pin so the two aren't quite forward compatible.


"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
news:400081BD.7090104@flukenetworks.com...
> Rene Tschaggelar wrote:
> > I started reading some documents about the configuration
> > devices EPCS1 & EPCS4. They appear to be programmed with a
> > new download cable, the Byteblaster2.
> > The Byteblaster2 claims compatibility with the previous models,
> > the Byteblaster and the ByteblasterMV. Unfortunately, there
> > is no schematics included in the Byteblaster2 datasheet.
> > Is the 74HC244 being changed to a 74LV244 this time ?
>
> Byteblaster2 is a superset of MV -- more than a buffer.
> But I expect that the MV can program an EPCS1.
>
>            -- Mike Treseler
>



Article: 64670
Subject: Re: Spartan-3 LC Development Kit from Insight (Memec)
From: Ralph Malph <noone@yahoo.com>
Date: Sun, 11 Jan 2004 01:32:59 -0500
Links: << >>  << T >>  << A >>
remis norvilis wrote:
> 
> I'm considering to get Spartan-3 LC Dev. Kit (DS-KIT-3SLC400) from Insight.
> Anybody used it? Comments would be appreciated.
> 
> Remis

I couldn't find anything on the Insight web site about this.  Where did
you see the info?

Article: 64671
Subject: Re: Spartan-3 LC Development Kit from Insight (Memec)
From: Remis Norvilis <Norvilis@charter.net>
Date: Sun, 11 Jan 2004 01:49:53 -0600
Links: << >>  << T >>  << A >>
And then Ralph Malph wrote:

> remis norvilis wrote:
>> 
>> I'm considering to get Spartan-3 LC Dev. Kit (DS-KIT-3SLC400) from
>> Insight. Anybody used it? Comments would be appreciated.
>> 
>> Remis
> 
> I couldn't find anything on the Insight web site about this.  Where did
> you see the info?

Check this site:
http://legacy.memec.com/devkits/americas.shtml

Article: 64672
Subject: Re: Dedicated CLK lines in CPLD
From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
Date: Sun, 11 Jan 2004 12:03:17 +0200
Links: << >>  << T >>  << A >>
> If you aren't short of product
> terms, you can just leave it as it is.

But poster above claims it is a bad design practice.

"Two architectors have ususally three opinions."



Article: 64673
Subject: Re: FPGA Size
From: "Yttrium" <Yttrium@pandora.be>
Date: Sun, 11 Jan 2004 14:59:11 GMT
Links: << >>  << T >>  << A >>
look at the synthesis report (of throught the floorplanner)...

"Chris" <Chris@nospam.com> wrote in message
news:btmpv0$5on$1@news5.svr.pol.co.uk...
> Hi
>
> I've done a design in VHDL using the XILINX software and I was wondering,
> how can I tell how much of the FPGA my design uses?  I was hoping I would
be
> able to find out what percentage of the FPGA my design uses.
>
> Thanks,
>
>



Article: 64674
Subject: Xilinx ISE6.1 Verilog `define macro?
From: Hakjs <Khak@hja.com>
Date: Sun, 11 Jan 2004 17:38:05 GMT
Links: << >>  << T >>  << A >>
I tried something like

`define MINIMUM2(x,y)  (((x)<(y))?(x):(y))
`define MINIMUM3(x,y,z) `MINIMUM2(`MINIMUM2(x,y),z)

This worked fine in Modelsim Verilog simulator, but Xilinx ISE6.1i's
XST (synthesis) didn't seem to like it...

Am I doing something wrong?




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