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Messages from 64500

Article: 64500
Subject: Re: 4-bit binary divider circuit PLEASE!!!!!!!
From: Paul Burke <paul@scazon.com>
Date: Tue, 06 Jan 2004 08:13:44 +0000
Links: << >>  << T >>  << A >>
YD wrote:
> 
> But the OP wanted to use only NAND gates. Oh well, an inverter on each
> input will turn an OR to a NAND, and as we're already spending
> transistors by the bucket might as well go for it.
> 
>

Easier than that, just define Vcc(ish) as 0 and ground(ish) as 1.

Paul Burke


Article: 64501
Subject: Re: XST cant compile with blaxkboxes.
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Tue, 6 Jan 2004 16:21:10 +0800
Links: << >>  << T >>  << A >>
MyProj\xst\work\vlg## latency?

I found that, if I perform re-synthesis after deleted some modules from
my source codes, the MyProj\xst\work\vlg## doesn't reflect this change.
As a result, at re-synthesis, even if I have a question mark on some
modules,
meaning the module source files are absent, the XST is still able to
synthesize
the design, does it mean it searches the MyProj\xst\work\vlg## to look for
the
missing modules?

Hope somebody can explain this mystery...

Best Regards,
Kelvin


Kelvin @ SG <kelvin8157@hotmail.com> wrote in message
news:3ffa04a7$1@news.starhub.net.sg...
> Hi, there:
>
> I am using ISE6.1 in office and ISE6.1Webpack at home. Both have service
> park 3 I think.
>
> How come on Webpack, I can synthesize with XST and instantiate black boxes
> at top level,
> however in original ISE6.1 it gave me error, complaining the that it can't
> find the bm_4b_v2...
> The bm_4b_v2 is in the same running directory.
>
> ERROR:HDLCompilers:87 - ../hdl/top_bt.v line 487 Could not find
> module/primitive 'bm_4b_v2'
>
> Is there any settings for XST to read in NMC macros as blackboxes?
>
> Could anybody teach me how to handle this situation?
>
> Best Regards,
> Kelvin
>
>
>



Article: 64502
Subject: Re: Xilinx Logicore PCI64 Problem
From: kanglc@starhub.net.sg (owner)
Date: 6 Jan 2004 01:01:12 -0800
Links: << >>  << T >>  << A >>
Hi,

Thanks everyone for your help.

I've found the problem. I was using a newer version of the
PCI logicore than that which my ISE can support. I don't
know why, but ngdbuild crashes with an "abnormal program
termination", saying it cannot find the ngo file.

After I downloaded an older version of the PCI core,
it works.

Regards,
LC

kanglc@starhub.net.sg (owner) wrote in message news:<265f36a.0401041841.14caff4a@posting.google.com>...
> Hi,
> 
> I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE
> 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a.
> NGDBUILD, the design, I encounter the following errors:
> 
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD'
>    in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;'
> 
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD'
>    in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;'
> 
> ERROR:NgdBuild:393 - Could not find INST(S)
> 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD'
>    in design 'gefsc_top'. INST entry is 'INST
> "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;'
> 
> The error continues for the whole bus width, and for other signals as
> well.
> I think the ucf file specifies the constraints using "/" to reference
> the instance, but the core instantiates in a different way. There is a
> file by the name of "pci_lc_i.vhd" which I found the instance
> PCI_AD64_IO31_OFD instantiated as:
> 
> PCI_AD64_IO31_OFD : X_FF
> port map(
> .....
> 
> Does this mean I have to change the ucf file's constraint statements?
> Can anyone in the group who has used xilinx logicore pci64 advice me
> on this?
> 
> Any help is greatly appreciated.
> 
> Regards,
> LC

Article: 64503
Subject: Re: Hyperthreading vs. Dual proc
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 06 Jan 2004 10:57:49 +0000
Links: << >>  << T >>  << A >>
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:

> On 05 Jan 2004 10:14:01 +0000, Martin Thompson
> <martin.j.thompson@trw.com> wrote:
> 
> >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:
> >> 
> >> The benefit of hyperthreading would be much more significant if there
> >> was only a single processor, or if there were lots of threads running.
> >> 
> >
> >I've found that enabling HT makes my machine useful for writing
> >documentation, reading email and other non-demanding tasks whilst PAR
> >is running.
> 
> It sounds like you have a single processor machine.  The differences
> are much less obvious on a multi-processor machine, and certain things
> (e.g. PAR) may be slower with hyperthreading enabled.
> 

This is true - more "real" hardware is always better, but the single
processor with hyperthreading amkes for a reasonably cheap
compromise.  I very rarely do anything where I could fully load a dual
processor box, hence justifying the cost would be tricky :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 64504
Subject: Re: Spartan3 availability
From: rtemple@arrowuk.com (Richard Temple)
Date: 6 Jan 2004 04:09:09 -0800
Links: << >>  << T >>  << A >>
jerry1111 <stop_this_spam_jerry1111_remove@remove.wp.pl> wrote in message news:<iga6uv87trtn31ftng213diohtdegv2d6m@4ax.com>...
> >Aye, but to be fair, how long has Cyclone been out now?
> 
> But you were able to buy small quantities early... not after
> a year - IMHO.

Also, dont forget that the Cyclone performs better in benchmarking
than SpartanIII in terms of power and raw clock speed, despite not
being 90nm...

Article: 64505
Subject: Re: Spartan3 availability
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 6 Jan 2004 12:26:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
Richard Temple <rtemple@arrowuk.com> wrote:
: jerry1111 <stop_this_spam_jerry1111_remove@remove.wp.pl> wrote 
: in message news:<iga6uv87trtn31ftng213diohtdegv2d6m@4ax.com>...
: > >Aye, but to be fair, how long has Cyclone been out now?
: > 
: > But you were able to buy small quantities early... not after
: > a year - IMHO.

: Also, dont forget that the Cyclone performs better in benchmarking
: than SpartanIII in terms of power and raw clock speed, despite not
: being 90nm...

How can you judge power and raw clock speed of Spartan III, while the parts
are not available yet?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 64506
Subject: Is the P&R processing time proportional to the FPGA gate count or the size of my logic?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Tue, 6 Jan 2004 21:01:51 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am performing active-module P&R for partial reconfiguration. My fixed
logic is 30K (ASIC) gates, and the
variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable
modules with a blackbox
for fixed module, how come it takes over 30 minutes but still ISE 6.1
couldn't finish this small module.

I want to know whether the P&R time is more related to my chip size OR the
size of my FPGA(Virtex2, 6000K).

Besides that, how may I derive the output file names in multi-pass P&R, e.g.
4_4_1.ncd from my par command
options?


Best Regards,
Kelvin




Article: 64507
Subject: Installation of Xlinx
From: "News sender" <renping.liu@eng.ox.ac.uk>
Date: Tue, 6 Jan 2004 13:08:20 -0000
Links: << >>  << T >>  << A >>
Hi,

I have just installed Xilinx5.1i on a pc running Win2000 with SP4. After the
installation and reboot the machine, the pc goes to the blue screen. I
reboot it again, it is still in the blue screen and I can't go to safe mode.

Has anyone seen this problem before?

Please help.

Regards

Renping Liu



Article: 64508
Subject: Questions about guard bits in CORDIC algorithm
From: freelait2000@yahoo.com (Jeff)
Date: 6 Jan 2004 06:18:17 -0800
Links: << >>  << T >>  << A >>
Hi,
I have learned about CORDIC from this group, especially from Ray. Now,
I have several more questions.
One paper described the implement structure of CORDIC algorithm. It
uses 16 bits data width and 6 guard bits internally. What is the guard
bits? I have borrowed several digital design books from library and
they do not mention that. Even though I can guess guard bits are used
for overflow prevention, it is far away from understanding the
utilization of its application in the CORDIC algorithm.
My another question is how to realize an MAC(multiply-and-accumulate)
and DAC(divide-and-accumulate) using CORDIC. The paper says they can.
Although I have read the relevant papers on the website of Ray, I have
not got the answer. Could you shed some light on this question?


Thans in advance

Article: 64509
Subject: Xilinx Virtex II Output Register
From: jcocozza@juno.com (jc)
Date: 6 Jan 2004 06:36:19 -0800
Links: << >>  << T >>  << A >>
I have a input signal thats get registered and then outputed on
another signal (pad) One register delay. I would like the Output
register to used instead of the Input register. I am using Xilinx ISE,
VHDL and a Virtex II device. Everytime I implement the Input register
is used, how do I use the Output register. I am trying to improve the
clock to pad time.

Thanks
John C

Article: 64510
Subject: Re: 4-bit binary divider circuit PLEASE!!!!!!!
From: Bob Stephens <stephensdigital@earthlink.net>
Date: Tue, 06 Jan 2004 14:53:50 GMT
Links: << >>  << T >>  << A >>
On Tue, 06 Jan 2004 08:13:44 +0000, Paul Burke wrote:

> YD wrote:
>> 
>> But the OP wanted to use only NAND gates. Oh well, an inverter on each
>> input will turn an OR to a NAND, and as we're already spending
>> transistors by the bucket might as well go for it.
>> 
>>
> 
> Easier than that, just define Vcc(ish) as 0 and ground(ish) as 1.
> 
> Paul Burke

Most of the DTL logic I worked with was "Negative NAND" logic. 0V = logic
0, -6V = logic 1.

Bob

Article: 64511
Subject: Re: Installation of Xlinx
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Tue, 6 Jan 2004 16:12:37 -0000
Links: << >>  << T >>  << A >>
Have a look at Xilinx's Answers Database specifically answer 14782
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=14782 .


John Adair
Enterpoint Ltd.
Xilinx Xperts Partner

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.

"News sender" <renping.liu@eng.ox.ac.uk> wrote in message
news:btec23$gsd$1@news.ox.ac.uk...
> Hi,
>
> I have just installed Xilinx5.1i on a pc running Win2000 with SP4. After
the
> installation and reboot the machine, the pc goes to the blue screen. I
> reboot it again, it is still in the blue screen and I can't go to safe
mode.
>
> Has anyone seen this problem before?
>
> Please help.
>
> Regards
>
> Renping Liu
>
>



Article: 64512
Subject: Re: Questions about guard bits in CORDIC algorithm
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Tue, 6 Jan 2004 16:24:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <6cdef69d.0401060618.706c7372@posting.google.com>, Jeff wrote:
> I have learned about CORDIC from this group, especially from Ray.

Me, too.  ;-)

> Now, I have several more questions.
> One paper described the implement structure of CORDIC algorithm. It
> uses 16 bits data width and 6 guard bits internally. What is the guard
> bits? I have borrowed several digital design books from library and
> they do not mention that. Even though I can guess guard bits are used
> for overflow prevention, it is far away from understanding the
> utilization of its application in the CORDIC algorithm.

Think of it this way: if you take 16 steps of CORDIC shift/conditional add,
each one of those adds round-off error.  If the computation is done with
16-bit precision, each one adds about one bit of round-off error, and
the error from 16 stages are uncorrelated, the net (rms) error for the
full computation is sqrt(16)*1 bit is 4 bits.  So your "16-bit" CORDIC
really only produces an answer that is 12-bit accurate.

I have CORDIC implemented in Verilog, and my test bench measures the
peak and rms error of the computation for a few thousand input vectors.
My data path is 16 bits, the input angle is 18 bits, and my actual test
bench output is

test covers 8205 points, full scale is 26980 bits
peak error   8.68 bits, 0.032 %
rms  error   2.09 bits, 0.008 %
PASS

> My another question is how to realize an MAC(multiply-and-accumulate)
> and DAC(divide-and-accumulate) using CORDIC. The paper says they can.
> Although I have read the relevant papers on the website of Ray, I have
> not got the answer. Could you shed some light on this question?

I don't see any relation between MAC/DAC and CORDIC.
Can you quote the relevant section of the paper?
Maybe you misread it.

     - Larry

Article: 64513
Subject: Re: Xilinx Virtex II Output Register
From: "Brannon King" <bking@starbridgesystems.com>
Date: 06 Jan 2004 11:51:48 EST
Links: << >>  << T >>  << A >>
Set IOB=FALSE on the input instance name and IOB=TRUE on the output instance
name, or use the primitives IBUF for the input buffer and OFDXI for the
output.


"jc" <jcocozza@juno.com> wrote in message
news:8e698b60.0401060636.6fc1d7a8@posting.google.com...
> I have a input signal thats get registered and then outputed on
> another signal (pad) One register delay. I would like the Output
> register to used instead of the Input register. I am using Xilinx ISE,
> VHDL and a Virtex II device. Everytime I implement the Input register
> is used, how do I use the Output register. I am trying to improve the
> clock to pad time.
>
> Thanks
> John C



Article: 64514
Subject: VirtexE DLL locked range
From: joey <>
Date: Tue, 6 Jan 2004 09:33:01 -0800
Links: << >>  << T >>  << A >>
Xilinx claimed that VirtexE DLL locks with input range 60-130 MHZ, my question is what's output clock
limitation? Suppose I have 25MHz input clock, the CLKDV will be 12.5MHZ? Does it violate anyhting?

Article: 64515
Subject: How do you initialize signals in VHDL?
From: madhuv_malladi@hotmail.com (Madhu)
Date: 6 Jan 2004 10:31:19 -0800
Links: << >>  << T >>  << A >>
Hello,
I understand that, initial values for signals are not supported for
synthesis. My problem is with the reset signal. For instance in the
below code,
***********************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity example  is
    port (
        clock: in STD_LOGIC;
        enable: in std_logic;
        datain: in STD_LOGIC;
        dataout:  out STD_LOGIC
    );
end gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is 
begin
   if(rising_edge(clock)) then  
         if(reset='1') then
         reset='0';
       end if;
        if(reset='0') then
        if(enable ='0') then 
         dataout<='0';
        end if;--enable
       if(enable='1')then
        dataout<=datain;
      end if;--enable 
        end if;--reset     
   end if;--rising edge 

end process;  
end example_arch;

I expect "reset" signal to be high for just one clock cycle, at the
start of the process and after the first clock cycle "reset" to be low
through out the process. That can expect to work for simulation if I
initialize reset signal to 1.
          signal reset:std_logic:='1';
But, it wouldn't help for synthesis. How can I tackle with this
situation ?

Thanks for your time…!!

Article: 64516
Subject: Re: How do you initialize signals in VHDL?
From: "valentin tihomirov" <valentinNOSPAM@abelectron.com>
Date: Tue, 6 Jan 2004 20:52:06 +0200
Links: << >>  << T >>  << A >>
if RESET = '1' then
    REG <= INIT;
elsif CLK'event and CLK = '1' then
    REG <= REG_NEXT;
end if;



Article: 64517
Subject: Re: Installation of Xlinx
From: "valentin tihomirov" <valentinNOSPAM@abelectron.com>
Date: Tue, 6 Jan 2004 20:54:06 +0200
Links: << >>  << T >>  << A >>
Why not to use latest version (6.1i, SP3)? I remember those blue screens.



Article: 64518
Subject: Re: fast mod (remainder) algorithm for V2?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 06 Jan 2004 11:00:48 -0800
Links: << >>  << T >>  << A >>
Brannon King wrote:
> I'm looking for a fast integer mod routine to be executed on a Virtex2-6000.
> Let's say 256bit unsigned integer divided by a 64bit unsigned integer where
> I only care about the remainder. Any ideas or directions? I don't care how
> many resources it uses. Thanks.


Virtex2 has built-in multipliers, so you could
loop on multiplying a loop count by the small
number and comparing that to the big number.

  --  Mike Treseler


Article: 64519
Subject: Re: Something additional: Adding internal signals in MODELSIM
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 06 Jan 2004 11:07:02 -0800
Links: << >>  << T >>  << A >>
ALuPin wrote:

> Maybe I should mention that I used megafunctions (RAM structures ... that
> I instantiated). 

Consider coding the RAM yourself
using the standard template.
This will allow you to sim your
code instead of a netlist.

     -- Mike Treseler


Article: 64520
Subject: Re: How do you initialize signals in VHDL?
From: Jim Lewis <Jim@SynthWorks.com>
Date: Tue, 06 Jan 2004 11:20:08 -0800
Links: << >>  << T >>  << A >>
 > I expect "reset" signal to be high for just one clock cycle, at the
 > start of the process and after the first clock cycle "reset" to be low
 > through out the process. That can expect to work for simulation if I
 > initialize reset signal to 1.
 >           signal reset:std_logic:='1';
 > But, it wouldn't help for synthesis. How can I tackle with this
 > situation ?

Reset needs to be an input to this block and generated
at one central source, typically outside your chip.
Typically reset will be active for several (100-1000) cycles
after power stabalizes.  A simple reset circuit is RC.
There are also some chips.

With this, reset becomes a board issue, not one you will
generate separately inside each block.

Best Regards,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



Madhu wrote:
> Hello,
> I understand that, initial values for signals are not supported for
> synthesis. My problem is with the reset signal. For instance in the
> below code,
> ***********************************************************
> library IEEE;
> use IEEE.std_logic_1164.all;
> 
> entity example  is
>     port (
>         clock: in STD_LOGIC;
>         enable: in std_logic;
>         datain: in STD_LOGIC;
>         dataout:  out STD_LOGIC
>     );
> end gsr;
> 
> architecture example_ arch of example is
> signal reset:std_logic;
> signal enable: integer range 0 to 10;
> begin
> process(clock,reset) is 
> begin
>    if(rising_edge(clock)) then  
>          if(reset='1') then
>          reset='0';
>        end if;
>         if(reset='0') then
>         if(enable ='0') then 
>          dataout<='0';
>         end if;--enable
>        if(enable='1')then
>         dataout<=datain;
>       end if;--enable 
>         end if;--reset     
>    end if;--rising edge 
> 
> end process;  
> end example_arch;
> 
> I expect "reset" signal to be high for just one clock cycle, at the
> start of the process and after the first clock cycle "reset" to be low
> through out the process. That can expect to work for simulation if I
> initialize reset signal to 1.
>           signal reset:std_logic:='1';
> But, it wouldn't help for synthesis. How can I tackle with this
> situation ?
> 
> Thanks for your time…!!


Article: 64521
Subject: Re: How do you initialize signals in VHDL?
From: Keith R. Williams <krw@attglobal.net>
Date: Tue, 6 Jan 2004 14:34:46 -0500
Links: << >>  << T >>  << A >>
In article <8f4cef63.0401061031.63a9c5f8@posting.google.com>, 
madhuv_malladi@hotmail.com says...
> Hello,
> I understand that, initial values for signals are not supported for
> synthesis. My problem is with the reset signal. For instance in the
> below code,
> ***********************************************************
> library IEEE;
> use IEEE.std_logic_1164.all;
> 
> entity example  is
>     port (
>         clock: in STD_LOGIC;
>         enable: in std_logic;
>         datain: in STD_LOGIC;
>         dataout:  out STD_LOGIC;
          reset:  in STD_LOGIC

You need a reset from somewhere else if you want to be guaranteed a 
state on power up.

>     );
> end gsr;
> 
> architecture example_ arch of example is
> signal reset:std_logic;
> signal enable: integer range 0 to 10;
> begin
> process(clock,reset) is 
> begin
>    if(rising_edge(clock)) then  
>          if(reset='1') then
>          reset='0';
I think you want to set dataout to 0, not reset.  You cannot set
>        end if;

No end if.  You want your process clocked, not just the reset.

>         if(reset='0') then
>         if(enable ='0') then 
>          dataout<='0';
>         end if;--enable

You're saying that if reset and enable are inactive you want the output 
to be '0'.  I don't think that's what you want.

>        if(enable='1')then
>         dataout<=datain;
>       end if;--enable 


You've now got a D latch (level sensitive) gated by not_reset and 
enable.  Actually you don't because if reset and enable are zero the 
output is '0' (from above), so you have a strange gate. ...with an edge 
triggered reset. ...not good.


>         end if;--reset     
>    end if;--rising edge 
> 
> end process;  
> end example_arch;

What you really want is more like:

***********************************************************
library IEEE;             
use IEEE.std_logic_1164.all;

entity example  is
    port (
        clock: in STD_LOGIC;
        enable: in std_logic;
        datain: in STD_LOGIC;
        dataout:  out STD_LOGIC;
        reset: in STD_LOGIC;            -- <-- ADDED
    );
end example;                             -- *NOT* gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is 
begin
   if(rising_edge(clock)) then  
        if(reset='1') 
            then          -- synchronous reset 
              dataout <='0';
          elsif(enable='1')
            then 
              dataout<=datain; 
        end if;--reset     
   end if;--rising edge clock 

end process;  
end example_arch;

Or if you'd rather have an asynchronous reset:

***********************************************************
library IEEE;             
use IEEE.std_logic_1164.all;

entity example  is
    port (
        clock: in STD_LOGIC;
        enable: in std_logic;
        datain: in STD_LOGIC;
        dataout:  out STD_LOGIC;
        reset: in STD_LOGIC;            -- <-- ADDED
    );
end example;                             -- *NOT* gsr;

architecture example_ arch of example is
signal reset:std_logic;
signal enable: integer range 0 to 10;
begin
process(clock,reset) is 
begin
   if reset = '1'
       then               -asynchronous reset
        dataout <= '0'
     elsif rising_edge(clock) 
       then  
         if(enable='1')
           then 
             dataout<=datain; 
         end if;--enable     
   end if; --reset 

end process;  
end example_arch;


> 
> I expect "reset" signal to be high for just one clock cycle, at the
> start of the process and after the first clock cycle "reset" to be low
> through out the process. That can expect to work for simulation if I
> initialize reset signal to 1.

Yes you have a synchronous reset (sorta), though it is reset on the 
rising edge of the clock.  You have some serious problems in this logic 
though (see above).

>           signal reset:std_logic:='1';
> But, it wouldn't help for synthesis. How can I tackle with this
> situation ?

You build a testbench that hooks to the architecture at a higher level 
(make this a component in your higher level implementation).  You put 
your simulation stuff in there and it doesn't get synthesized.

> 
> Thanks for your time…!!
> 

Article: 64522
Subject: Re: VirtexE DLL locked range
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 06 Jan 2004 11:42:00 -0800
Links: << >>  << T >>  << A >>
The output clock of CLK0 is exactly the same as the CLKIN.

CLKDV can be any value as listed (1.5, 2, 2.5, 3, 4.....) (divisor of 
CLKIN).

So if CLKDV=2 (divide by two) everything is legal for a CLKIN of 25 MHz.

Austin

joey wrote:
> Xilinx claimed that VirtexE DLL locks with input range 60-130 MHZ, my 
> question is what's output clock
> limitation? Suppose I have 25MHz input clock, the CLKDV will be 12.5MHZ? 
> Does it violate anyhting?


Article: 64523
Subject: Re: Spartan3 availability
From: Ralph Malph <noone@yahoo.com>
Date: Tue, 06 Jan 2004 16:02:18 -0500
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> 
> Richard Temple <rtemple@arrowuk.com> wrote:
> : jerry1111 <stop_this_spam_jerry1111_remove@remove.wp.pl> wrote
> : in message news:<iga6uv87trtn31ftng213diohtdegv2d6m@4ax.com>...
> : > >Aye, but to be fair, how long has Cyclone been out now?
> : >
> : > But you were able to buy small quantities early... not after
> : > a year - IMHO.
> 
> : Also, dont forget that the Cyclone performs better in benchmarking
> : than SpartanIII in terms of power and raw clock speed, despite not
> : being 90nm...
> 
> How can you judge power and raw clock speed of Spartan III, while the parts
> are not available yet?

I thought that information was in all the press releases!  :)

Article: 64524
Subject: readback spartan2e
From: silviai@argentina.com (Turquesa)
Date: 6 Jan 2004 13:17:09 -0800
Links: << >>  << T >>  << A >>
I am working with a spartan2e and i wish readback the register, not my
configuration, i read that is posible, i am using iMPACT and it have a
option READBACK, but is always disenable.
Any help is welcome
thanks, Silvia



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