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Messages from 3775

Article: 3775
Subject: BIDIR Buses
From: Alex Krynew <jmacow@dol.ru>
Date: Tue, 30 Jul 1996 02:28:18 +0400
Links: << >>  << T >>  << A >>
Hi,
Here is quite simple problem I didn't find solution yet.

How to implement bidirectional tri-state buses inside FPGA design?
I use XACT 6.0/ Viewlogic Schematic Interface.

Any help or advises are wellcome.
Thank You.
Alex.
Article: 3776
Subject: Question: FPGA versus ASIC design.
From: hajimow@engn.uwindsor.ca (Hajimowlana-Hossain)
Date: Tue, 30 Jul 1996 01:06:19 GMT
Links: << >>  << T >>  << A >>
	What is the efficiency of ASIC design versus FPGA design.I know that lots of
silicon area is used for switches and connection lines in FPGA but is there any number
that can show the efficiency based on silicon area ?eg. 10 or 15 .

thanks

Hossain

Article: 3777
Subject: Re: BIDIR Buses
From: MarkW@rmcecl.demon.co.uk (Mark Webster)
Date: Tue, 30 Jul 1996 15:14:44 GMT
Links: << >>  << T >>  << A >>
Alex Krynew <jmacow@dol.ru> wrote:

>Hi,
>Here is quite simple problem I didn't find solution yet.

>How to implement bidirectional tri-state buses inside FPGA design?
>I use XACT 6.0/ Viewlogic Schematic Interface.

>Any help or advises are wellcome.
>Thank You.
>Alex.

Just draw the busses as you would for a normal tri-state bus and use 
TBUF modules to gate the appropriate data onto the bus.

Mark

Article: 3778
Subject: Re: ATT serial EEPROMs
From: Tom Burgess <tburgess@drao.nrc.ca>
Date: Tue, 30 Jul 1996 10:01:58 -0700
Links: << >>  << T >>  << A >>
Lawrence Butcher wrote:
> 
> AT&T flash serial proms observed to fail to configure reliably at powerup.
> 
> I have had the exact same experience with AT&T serial proms.  They work fine
> if the power supply comes up fast, and don't configure if it comes up slow.
> 

I am curious as to whether people with ATT SPROM config problems are
using the active low RESET option, (RESET*), with RESET* driven by the 
lead FPGA INIT* output. According to the Xilinx databook ('94, p2-233) 
this removes the issue of the relative timing of FPGA/SPROM power-on
reset and is generally recommended. Please inform me if the problem
exists with this connection and I will be appropriately cautious about 
ATT SPROMS in future. Thanks -

		 Tom Burgess tburgess@drao.nrc.ca
Article: 3779
Subject: new thread, was: Question: FPGA versus ASIC design.
From: eteam@aracnet.com (bob elkind)
Date: Tue, 30 Jul 1996 20:39:45 +0100
Links: << >>  << T >>  << A >>
In article  peter@xilinx.com says...
> >         is there any number
> > that can show the efficiency based on silicon area ?eg. 10 or 15 .
> > 
> Why do you care?

He's learning, go easy on him!

> Usually, FPGA chips are substantially bigger than equivalent capacity
> ASICs, but there are several factors that help FPGAs:

> FPGAs are mass-produced and move as fast as possible to a new, more
> efficient process technology= smaller chip. ASICs usually stay with their
> original design for cost reasons.

FPGAs *AND* ASICS (both) move as fast as *practical* to a newer, whizzy
process.  You can't honestly say that 4000EX FPGAs are built on a
process equivalent to Pentium Pros!  I don't see how FPGAs have any
inherent "edge" in migrating up the processing food chain.  I *would*
believe that standard cells can be had in faster/whizzier processes
*sooner* than FPGAs.

And sure, once the ASIC is designed in process X, it tends to stay in
process X for its lifetime, and sooner or later FPGAs overtake the
process X in which the ASIC was originally cast.  But keep in mind
that the ASIC (std cell or gate array) has a head start.

Case in point:  Xilinx' own HardWire product/service...
lower cost per gate, better AC performance, lower power...

 -- yup, even with the exact same process, you can get better results
in these three areas just by going semi-custom.

> FPGAs are mass produced and travel down the manufacturing learning curve
> faster than ASICs.

Interesting thought.  I don't believe it.  Without getting too bogged
down in the definition of "ASIC", most of the big guys (e.g. Moto, TI,
Intel) do their humongous work in the same ASIC technology and process
steps as the rest of us.  They can't afford to do hand layout on every
little via and metal run and transistor.  They're doing cell-based
design.

> Finally, low-complexity but high pin-count devices might be "pad-limited",
> which means their die size is dictated by the number of IO, not the logic.
> In that case there may be no size difference between the two.

> It's not a matter of square mm, it's a matter of cost. An that has far
> more variables than just chip size.

Agreed.

> Peter Alfke, Xilinx Applications.

Peter, we've known each other for a long time, and I respect your
opinions greatly.  Your comments just yanked my chain, on this topic.

I've done lots of custom, semi-custom, and FPGAs.  Having just told
Peter to be "not quite so proud" of his FPGAs, most of the design
work I do these days *is* in FPGAs (not ASICs).

ASICs are still way ahead of FPGAs in some technical and cost areas,
but nothing beats the low risk and engineering cost of FPGAs.

I love you Peter, but you can't have my Bud Lite.

Bob

**************************************************************************
Bob Elkind                mailto:eteam@aracnet.com            CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************
Article: 3780
Subject: Re: Question: FPGA versus ASIC design.
From: peter@xilinx.com (Peter Alfke)
Date: Tue, 30 Jul 1996 15:58:50 -0700
Links: << >>  << T >>  << A >>
In article <DvC0EJ.5vv@news.uwindsor.ca>, hajimow@engn.uwindsor.ca wrote:

>         is there any number
> that can show the efficiency based on silicon area ?eg. 10 or 15 .
> 
Why do you care?
Usually, FPGA chips are substantially bigger than equivalent capacity
ASICs, but there are several factors that help FPGAs:
FPGAs are mass-produced and move as fast as possible to a new, more
efficient process technology= smaller chip. ASICs usually stay with their
original design for cost reasons.
FPGAs are mass produced and travel down the manufacturing learning curve
faster than ASICs.
Finally, low-complexity but high pin-count devices might be "pad-limited",
which means their die size is dictated by the number of IO, not the logic.
In that case there may be no size difference between the two.

It's not a matter of square mm, it's a matter of cost. An that has far
more variables than just chip size.


Peter Alfke, Xilinx Applications.
Article: 3781
Subject: Re: Clearing security fuse on Lattice ispLSI2032?
From: trev@ss11.wg.icl.co.uk (Trevor Hall)
Date: 31 Jul 1996 05:36:36 GMT
Links: << >>  << T >>  << A >>
In article <4tav6m$4lb@transfer.stratus.com>, Matt Cross
<mcross@sw.stratus.com> writes
>I purchased a copy of Lattice's ISP starter kit, and I am just toying with
>programming teh 2032 part.  I got a PLCC adapter that I've plugged into
>my breadboard, and have wired up the programming cable.  The programming
>software ('Daisy Chain Download') that came with the kit recognizes the
>chip, and says it succesfully programmed it, but that it cannot verify
>it because the security fuse is set.  But, when I generated the fuse map
>(.JED file) I told it to not set the security fuse.  My design does not
>appear to be in the device from my simple tests.
>
>Any ideas?  Am I just destroying the signals by running it on a breadboard?
>
>(In case you coudln't tell, I'm not a real hardware guy, I mostly do software.
> I find digital logic fascinating, though, and I wanted to try it out...)
>
>       -Matt

Check out your power supply voltages. I had a similar problem verifying 3256 devices
on low (or was it high) margins.
That said the devices do function correctly, once programmed, over the specified 
supply voltage range.

T.H.














Article: 3782
Subject: Multi-FPGA Partitioners?
From: "J. A. Herrera Camacho" <herrera@die.upm.es>
Date: Wed, 31 Jul 1996 14:37:00 +0200
Links: << >>  << T >>  << A >>
Hello!

I am currently working on a multi-FPGA project with XC4000 FPGAs.
I have to face the problem of partition a design among several FPGAs.

My questions are:

- Which is the current state of the art in this problem?

- Is there any comercial software for it? Does Xilinx plan to provide
one?

- Is there any free partitioner available?

I will post an abstract of the answers that I get.

Thank you.

Regards.

J. A. Herrera Camacho.
Article: 3783
Subject: assigning LOC in XACT
From: tw38966@vub.ac.be (Rafiki Kim Hofmans)
Date: 31 Jul 1996 17:15:55 GMT
Links: << >>  << T >>  << A >>
Hi,

can someone tell me how I can assign LOCs to a 16 bit IOPAD in the Xilinx
schematic entry ?
I suppose I have to make a file with the LOCs.

Or is the only solution using 16 times 1 IOPAD ? :(

Thanks in advance !

Kim
--


==============================================================================

			************************************
			*	Hofmans Kim 		   *	
  		       	*				   *
			*	tw38966@vub.ac.be	   *
			*	khofmans@info.vub.ac.be	   *
			*                                  *
			*	Brouwerijstraat 62         *
			*	1630 Linkebeek             *
			*	Belgium 		   *
			*				   *
			*	32-2-3771012		   *
			*				   *
			************************************

Article: 3784
Subject: Re: Job posting
From: jcooley@world.std.com (John Cooley)
Date: Wed, 31 Jul 1996 18:27:12 GMT
Links: << >>  << T >>  << A >>
HighTech <hightech@mv.mv.com> wrote:
>
>Are we going to start posting job listings to these newsgroups?
>

Please don't.  Job postings are for the job newsgroups.  Once the
headhunters start massively job posting in the technical newsgroups,
it effectively kills the technical discussions in the newsgroups
because it turns off too many engineers.

It's all a matter of signal-to-noise; what does the fact that 8
different headhunters posting and reposting "HOT JOBS AT SGI!!!"
have to do with my getting a solution to the EDA bug I'm currently
fighting?  Nothing.
                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3785
Subject: Re: Question: FPGA versus ASIC design.
From: ft63@dial.pipex.com (Peter)
Date: Wed, 31 Jul 1996 20:14:19 GMT
Links: << >>  << T >>  << A >>


>	What is the efficiency of ASIC design versus FPGA design.I know that lots of
>silicon area is used for switches and connection lines in FPGA but is there any number
>that can show the efficiency based on silicon area ?eg. 10 or 15 .

In general, when moving from an FPGA to an ASIC, you end up using a
lot fewer gates than you expected. I have recently ported a 60%-full
XC3090 design to an ASIC, and it uses only about 2000 gates. I would
think the ASIC chip is much smaller than that of a 3090, but does this
matter?

You also gain a lot in dynamic power consumption. This is largely
because you don't have the global clock nets, and you can gate clocks
much more freely than one is able to in an FPGA. FPGA design tends to
make use of the global clock nets, and you use the clock enables on
individual D-types to decide which one gets clocked. In my above
design, dynamic Icc dropped from 15-20 mA (and that was a XC3042,
implementing a subset of the 3090 design) to about 1-2mA. However,
this amount of power saving may not come if you just go to a straight
netlist port like e.g. Orbit offer.

But ASIC NREs and minimum quantities are much more demanding than they
were in the ASIC heyday of some years ago. The only exceptions are the
several firms around who can take your Xilinx netlist, but I have
never used them for other reasons.

Peter.
Article: 3786
Subject: Re: assigning LOC in XACT
From: Andy Gulliver <andy.gulliver@crossprod.co.uk>
Date: Thu, 01 Aug 1996 09:11:19 +0100
Links: << >>  << T >>  << A >>
I think you'll have to assign 16 IOPADs - if you find an easier way, 
please let me know.
-- 
Regards

AndyG
Article: 3787
Subject: ANNOUNCE: FREE Model of the Month - IPCRA
From: Rob Hurley <rob@doulos.co.uk>
Date: Thu, 01 Aug 1996 17:48:05 GMT
Links: << >>  << T >>  << A >>


ANNOUNCEMENT: Immediate Release


		 Model of the Month
		====================

This month's FREE model is:

	
	Image Processing Cache Register Array


You can find it at http://www.doulos.co.uk. 

You can also access previous FREE Models and Tips of the Month from 
the same site.
____________________________________________________________________

Also *** NEW *** for this month are:

	TIP of the MONTH:  Encapsulation in VHDL

	Excerpts from the VHDL Golden Reference Guide

	Additions to our 'Hardware Engineers Guide to VHDL' series
	
____________________________________________________________________

Also visit the Doulos site 'THE WINNING EDGE' for:
	
	
	VHDL Quick Reference Card
	
	VHDL 93 Update Reference Card


_____________________________________________________________________

Also details how to get a FREE online VHDL tutorial.

	
DOULOS
Church Hatch				Tel: +44 1425 471 223
22 Market Place				Fax: +44 1425 471 573
Ringwood BH24 1AW			Email: info@doulos.co.uk
UK

_____________________________________________________________________


Article: 3788
Subject: ANNOUNCE: New FREE Tip of the Month - Encapsulation
From: Rob Hurley <rob@doulos.co.uk>
Date: Thu, 01 Aug 1996 17:53:28 GMT
Links: << >>  << T >>  << A >>

ANNOUNCEMENT: Immediate Release


		 Tip of the Month
		==================

This month's FREE 'Tip' is:

	
	Encapsulation in VHDL


You can find it at http://www.doulos.co.uk. 

You can also access previous FREE Models and Tips of the Month from 
the same site.
____________________________________________________________________

Also *** NEW *** for this month are:

	FREE MODEL of the MONTH:  Image Processing Cache Register
				  Array
	
	Excerpts from the VHDL Golden Reference Guide

	Additions to our 'Hardware Engineers Guide to VHDL' series
	
____________________________________________________________________

Also visit the Doulos site for:
	
	
	VHDL Quick Reference Card
	
	VHDL 93 Update Reference Card


_____________________________________________________________________

Also details of how to get a FREE online VHDL tutorial.


DOULOS
Church Hatch				Tel: +44 1425 471 223
22 Market Place				Fax: +44 1425 471 573
Ringwood BH24 1AW			Email: info@doulos.co.uk
UK					URL:  http://www.doulos.co.uk

_____________________________________________________________________

Article: 3789
Subject: Reconfigurable Hardware
From: Pasquale Corsonello <pascor@ccusc1.unical.it>
Date: Thu, 01 Aug 1996 11:11:27 -0700
Links: << >>  << T >>  << A >>
Hi all

I'm looking for papers deal with the use of reconfigurable hardware in
arithmetic circuit. In particular, the use of SRAM-based FPGA for 
reconfigurable arithmetic circuit is intersting for me; such as SRT
based divide/square root circuit.
Please, anyone has reference reply me.

Pasquale Corsonello
Dept. of Electronic Computer Science and System
University of Calabria
e-mail:pascor@ccusc1.unical.it
       corsone@nwdeis1.unical.it
Article: 3790
Subject: US-NH FPGA Design Engineer, Avionics
From: Kevin Hawes <khawes@cadstar.com>
Date: Thu, 01 Aug 1996 16:02:11 -0400
Links: << >>  << T >>  << A >>
Reference Number: 	1000417

Title:			FPGA Design Engineer, Avionics

Location:		NH

Type:			Permanent

Salary:			Open, relative to experience

Description:

Design and develop electronic circuits that will be primarily digital
with some custom components including FPGAs and/or ASICs. Designs may
involve processors, data bus interfaces, combinatorial functions, and
aircraft or spacecraft interfaces. The design process will include
simulations using state of the art tools. 

Experience:

Experience with simulation tools, FPGAs and/or ASICs is a plus. BS
degree in Electronic Engineering from an accredited college/university
or its equivalent. Must be a US citizen.

If interested e-mail a TEXT file format of your resume to:
khawes@cadstar.com

or mail/FAX to:

Kevin T. Hawes
CADstar International
130 Middlesex Road, PO Box 704
Tyngsboro, MA 01879

Phone: (508)649-6828  FAX: (508)649-7856  e-mail: khawes@cadstar.com
Article: 3791
Subject: US-NH FPGA Computer Architecture Design Engineer
From: Kevin Hawes <khawes@cadstar.com>
Date: Thu, 01 Aug 1996 16:04:07 -0400
Links: << >>  << T >>  << A >>
Reference Number:       1000420
 
Title:                  FPGA Computer Architecture Design Engineer
 
Location:               NH 
 
Type:                   Permanent 
 
Salary:                 Open, relative to experience 
  
Description: 
  
Demonstrated capability as a technical lead in advanced computer
architecture, complex digital module and FPGA design, VHDL simulation,
VHDL synthesis and working with emerging CAE technology a must.
Processor design experience must include evaluating processing functions
vs. architecture schemes for various signal and image processing
applications.

Experience:

Experience in the innovative use of reconfigurable computing for  image
processing, and signal processing is a plus. The new ECAE technology to
be used for this effort must become refined for broader use. BS in
Electronic Engineering from an accredited college/university or its
equivalent and 8 years work experience; or a MS and 7 years experience;
or a Ph.D. with 4 years experience.

If interested e-mail a TEXT file format of your resume to:
khawes@cadstar.com

or mail/FAX to:

Kevin T. Hawes
CADstar International
130 Middlesex Road, PO Box 704
Tyngsboro, MA 01879

Phone: (508)649-6828  FAX: (508)649-7856  e-mail: khawes@cadstar.com
Article: 3792
Subject: Re: US-NH FPGA Design Engineer, Avionics
From: jcooley@world.std.com (John Cooley)
Date: Fri, 2 Aug 1996 05:30:16 GMT
Links: << >>  << T >>  << A >>
>Reference Number: 	1000417
>Title:			FPGA Design Engineer, Avionics
>Location:		NH
>Type:			Permanent
>Salary:			Open, relative to experience
>
>Description:
>
>Design and develop electronic circuits that will be primarily digital
>with some custom components including FPGAs and/or ASICs. Designs may
>involve processors, data bus interfaces, combinatorial functions, and
>aircraft or spacecraft interfaces. The design process will include
>simulations using state of the art tools. 


This one's easy; it's Lockheed-Sanders up in New Hampshire.  I even
know the engineers up there!  If anyone's is looking for a job
there, blow off this headhunter and send your resumes to me.  I'll
forward them to the engineers there and they can get the referal
bonus!  (Or if you want to send your resume up to their HR dept.,
call (603) 555-1212 and ask for "Lockheed-Sanders".)

Why can't these headhunters post in the job newsgroups?

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3793
Subject: Re: assigning LOC in XACT
From: raghu@cse.iitb.ernet.in (Raghavendra G Jorapur)
Date: Fri, 2 Aug 1996 06:36:58 GMT
Links: << >>  << T >>  << A >>
Rafiki Kim Hofmans (tw38966@vub.ac.be) wrote:
: Hi,
: 
: can someone tell me how I can assign LOCs to a 16 bit IOPAD in the Xilinx
: schematic entry ?
: I suppose I have to make a file with the LOCs.
: 
: Or is the only solution using 16 times 1 IOPAD ? :(
: 
: Thanks in advance !
: 
: Kim
: --

u can also specify in a constranits file ( .cst )
for syntax look into the XACT manuals.
-Raghu
Article: 3794
Subject: Re: US-NH FPGA Design Engineer, Avionics
From: markc@gibelet.nexen.com (Mark Christensen)
Date: 2 Aug 1996 11:09:52 -0400
Links: << >>  << T >>  << A >>

I second John's opinion. I can submit the resume for you and let 
an employee get the referral. Maybe the headhunters will get the message and 
stop posting in this newsgroup.



In article <DvHwMG.AJK@world.std.com>, jcooley@world.std.com (John Cooley) writes:
|> >Reference Number: 	1000417
|> >Title:			FPGA Design Engineer, Avionics
|> >Location:		NH
|> >Type:			Permanent
|> >Salary:			Open, relative to experience
|> >
|> >Description:
|> >
|> >Design and develop electronic circuits that will be primarily digital
|> >with some custom components including FPGAs and/or ASICs. Designs may
|> >involve processors, data bus interfaces, combinatorial functions, and
|> >aircraft or spacecraft interfaces. The design process will include
|> >simulations using state of the art tools. 
|> 
|> 
|> This one's easy; it's Lockheed-Sanders up in New Hampshire.  I even
|> know the engineers up there!  If anyone's is looking for a job
|> there, blow off this headhunter and send your resumes to me.  I'll
|> forward them to the engineers there and they can get the referal
|> bonus!  (Or if you want to send your resume up to their HR dept.,
|> call (603) 555-1212 and ask for "Lockheed-Sanders".)
|> 
|> Why can't these headhunters post in the job newsgroups?
|> 
|>                            - John Cooley
|>                              Part Time EDA Consumer Advocate
|>                              Full Time ASIC, FPGA & EDA Design Consultant
|> 
|> ===========================================================================
|>  Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
|>  users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
|>  
|>       !!!     "It's not a BUG,               jcooley@world.std.com
|>      /o o\  /  it's a FEATURE!"                 (508) 429-4357
|>     (  >  )
|>      \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
|>      _] [_         Verilog, VHDL and numerous Design Methodologies.
|> 
|>      Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
|>    Legal Disclaimer: "As always, anything said here is only opinion."
-- 
Mark Christensen				       ascom-Nexion
email: markc@nexen.com				       289 Great Road
ph: (508) 266-2315				       Acton, MA 01720

Article: 3795
Subject: Re: Clearing security fuse on Lattice ispLSI2032?
From: mcross@sw.stratus.com (Matt Cross)
Date: 2 Aug 1996 19:42:19 GMT
Links: << >>  << T >>  << A >>
In article <qKWR+DAAxi+xEwJ4@tennyson.demon.co.uk>,
	Nigel Burrows <nigel@tennyson.demon.co.uk> writes:
>The first circuit I built didn't include the .01uF capacitor between
>!ispEN and ground which caused the verification to fail.
>
>I've used the 2032 with a home made PLCC to DIL adaptor on a breadboard
>OK.

Thanks everybody for your help.  I had a capactitor in the right place, but
it was too small (silly software engineers who can't read capactitors :-) ).
Once I put the right cap in there it worked great.

	-Matt


Article: 3796
Subject: Xilinx/FPGA Timing Problems
From: jeffh@oakhill-csic.sps.mot.com (Jeff Hunsinger)
Date: 2 Aug 1996 21:05:42 GMT
Links: << >>  << T >>  << A >>
I'm sure I'm not the only one battling these problems, so I thought I'd put
out a general call for help:

I'm using Neocad (Xilinx) Foundry 7.0 software to place & route a synthesized
design into 3195A and 40xx series parts. Neocad seems to be the weak link in
the flow. Sometimes I have a design that works fine until I modify some other,
unrelated part of the circuit. When the design is re-routed, it will cease to
work. These are often fairly simple, synchronous designs.

My usual strategy is to insert clock buffers on critical clock lines, use
FREQUENCY NET and FREQUENCY constraints in the device.prf files, and make slight
modifications to the top level HDL so the synthesized schematic will be slightly
different (causing Neocad to route a slightly different design, hopefully with
better results).

This approach seems crude at best. I've thought about trying to use floorplanning,
but I haven't attempted it yet for two reasons:

1. Synthesized schematics are usually very difficult to decipher.
2. When I can make sense of the signals (usually on smaller designs), the placement
   looks like it makes sense (all the flip-flops in a counter chain are located
   in the same area, for example).

I do have a number of constraints on my system. Many of my I/O pins are constrained,
which ends up limiting me to about 50-60% utilization.

Anyone have any suggestions for how I can consistently get reliable timing results?

Thanks,
Jeff Hunsinger

----------------------------------------------------------------------

Jeff Hunsinger
jeffh@oakhill-csic.sps.mot.com

Article: 3797
Subject: Re: Question: FPGA versus ASIC design.
From: hajimow@engn.uwindsor.ca (Hajimowlana Hossain)
Date: Fri, 2 Aug 1996 23:00:25 GMT
Links: << >>  << T >>  << A >>
> > >         is there any number
> > > that can show the efficiency based on silicon area ?eg. 10 or 15 .
> > > 
> > Why do you care?
> 
> He's learning, go easy on him!
> 
> > Usually, FPGA chips are substantially bigger than equivalent capacity
    ^^^^^^^^
> > ASICs, but there are several factors that help FPGAs:

Thanks alot for the responses to my question.Yes I am learning .umm.. it is 
interesting, You say "Usually" , and my impression is it means "not always".So another
question rises.In what designs FPGA chips are smaller than ASICS? Is it for the 
designs with higher number of inputs?

Hossain



Article: 3798
Subject: Re: Xilinx/FPGA Timing Problems
From: ft63@dial.pipex.com (Peter)
Date: Sat, 03 Aug 1996 21:33:49 GMT
Links: << >>  << T >>  << A >>

I have only once ever seen a case where a design does not work, and a
straight recompilation "fixes" it, and that was recently with XACT6
place/route software.

But I have more often come across a nastier problem, common to all
FPGAs: say you have a 16-bit shift register. Obviously, for a SR to
work, the clock skew stage-to-stage has to be less than the clock-to-Q
propagation delay. IOW, you ideally want to clock all the stages
together.

The complex routing in an FPGA makes this hard to achieve. I generally
put a SC=1 attribute on any such clock nets (requesting a skew of 1ns
or less!) but this cannot be achieved when there are more than a few
stages.

The "proper" way to do this is to use one of the global clock nets to
clock all the D-types, and use clock enables to decide which actually
get clocked. Of course, in my above SR example, they all get clocked
together anyway, but you may still need to gate the clocks, otherwise
the SR will be shifting all the time!

Unless I am oversimplifying your problem, it is possible that this is
what you are seeing. Even if you do everything "synchronous", this is
where you get caught.

Incidentally, the problem with porting such an FPGA design to an ASIC
is that you may get an ASIC with a lot higher power consumption than
would be the case otherwise. This is one area where prototyping ASICs
in FPGAs (a near-universal practice nowadays in ASIC design) is
difficult.

Peter.
Article: 3799
Subject: Re: Question about books for FPGA
From: peter@xilinx.com (Peter Alfke)
Date: Sat, 03 Aug 1996 15:16:13 -0700
Links: << >>  << T >>  << A >>
In article <Pine.SUN.3.91.960729074337.16136A-100000@Bundy>, Rainer
Scharnow <amigo@bintec.de> wrote:

Of course, no 
> one describes the limitations of the products 8-).
> 
Did it ever occur to you that the only thing the parameter values in the
data sheet describearet device limitation?

Propagation delays describe that the output doesnt change instantaneously
Set-up and hold times tell you that the device may malfunction if you
change data during that timing window

Vcc describes that operation is only guaranteed between 4.75 and 5.25 V
Temperature ranges describe that parameters are only guaranteed for a
limited range of temperatures.
Max storage temperature, max soldering temperature, max leakage current,
and the list goes on...

The data sheet parameters do not describe how good the devices are, they
describe how "bad" they might be, in the extreme case.

Our industry gives you hundreds ( thousands ? ) of pages of product limitations.
I suppose you have never looked at it this way. :-)

Peter Alfke, Xilinx Applications


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