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Messages from 6675

Article: 6675
Subject: Sr. System Simulation Engineer,FPGA
From: "Robin M. Morneault" <rmorno@eden.com>
Date: Thu, 12 Jun 1997 14:33:44 -0700
Links: << >>  << T >>  << A >>
Title: Sr. System Simulation Engineer
Location: Austin, TX

Duties:  Help define/implement the verification methodology of complex
digital ICs.  Help develop high level Verilog system models, system 
simulation environment, and X86 assembly/behavrioral level test cases 
to thoroughly verif the system architecture at RTL/Gate level.

Requirements: BS/MS in EE/CS with 3 or more years of experience in
design, simulation, and debug of digital circuitry.  Strong background
in developing complex simulation models using a high level of behavioral/
RTL design language.  FPGA experience needed.  Verilog experience will 
have the edge.  Experience with system simulation environment, x86 based
pc architecture, ISDN, HDLC or USB communication technolgy is preferred.

-- 
Robin Morneault
Professional Recruiter 
Career Consultants Staffing Services
512-346-6660 voice
512-346-6714 fax
headhunter@eden.com
Career Consultants Staffing Services, Inc. has been professionally 
staffing for 25 years as a full service staffing firm that provides 
executive search, direct hire, contract, technical and temporary 
services.
Article: 6676
Subject: Engineer, FPGA
From: "Robin M. Morneault" <rmorno@eden.com>
Date: Thu, 12 Jun 1997 14:41:10 -0700
Links: << >>  << T >>  << A >>
Title:     Engineer II
Location:     Austin, TX 78741, USA

Description:
     Job requires a BS or MS degree, 1+ years of applicable experience.
     Knowledge of analog design, PCB design tools, and FPGA programming	
are desired. Knowledge of C or C++ and basic programming skills are an
     advantage. Good communication skills are required as are good design
     methodology and good decision making skills.

     JOB FUNCTIONS: Will entail the design and devlopment of tools and
     products to support communication products, focusing on the
     family of digital cordless phone ICs. This will include evaluation
     boards, interface circuits, and reference designs to enable 
     customers with "quick time-to-market" solutions. The job will 
involve
     interaction with customers that are in the phases of the design
     process, from early evaluation to final production ramp-up.

-- 
Robin Morneault
Professional Recruiter 
Career Consultants Staffing Services
512-346-6660 voice
512-346-6714 fax
headhunter@eden.com
Career Consultants Staffing Services, Inc. has been professionally 
staffing for 25 years as a full service staffing firm that provides 
executive search, direct hire, contract, technical and temporary 
services.
Article: 6677
Subject: Power consumption (Xilinx FPGA) questions
From: janovetz@coewl.cen.uiuc.edu (Jacob W Janovetz)
Date: 12 Jun 1997 23:13:28 GMT
Links: << >>  << T >>  << A >>
Hello,

   I'm wondering if anyone has any 'standard' values for power
consumption they use for Xilinx FPGAs.  The literature lists
consumption on a per-CLB basis which varies depending on the
programming.  However, mine are going into a reprogrammable
system and I really can't predict that much, but would like
near-maximum values for power supply consideration.  I'm 
looking for the 4028XL-3, 4010XL-3, 4006E-4 specifically,
but a general idea would serve me well, too.

    Thanks,

    Jake

 
--
janovetz@coewl.cen.uiuc.edu| Once you have flown, you will walk the earth with
   University of Illinois  | your eyes turned skyward, for there you have been,
                           | there you long to return.     -- da Vinci
          PP-ASEL          | http://www.cen.uiuc.edu/~janovetz/index.html
Article: 6678
Subject: Re: Power consumption (Xilinx FPGA) questions
From: Tom Burgess <Tom_Burgess@bc.sympatico.ca>
Date: Fri, 13 Jun 1997 00:45:21 -0700
Links: << >>  << T >>  << A >>
Jacob W Janovetz wrote:
> 
> Hello,
> 
>    I'm wondering if anyone has any 'standard' values for power
> consumption they use for Xilinx FPGAs.  The literature lists
> consumption on a per-CLB basis which varies depending on the
> programming.  However, mine are going into a reprogrammable
> system and I really can't predict that much, but would like
> near-maximum values for power supply consideration.  I'm
> looking for the 4028XL-3, 4010XL-3, 4006E-4 specifically,
> but a general idea would serve me well, too.
> 

FPGA power estimation is tricky, since you need to know the frequency
at which internal nodes are switching (design and data dependent)
and the power cost of each node. As far as I know there are no
good tools available from Xilinx or anyone for power estimation
on Xilinx parts. The scary part is that a worst-case design toggling
every node on a big part can EASILY exceed several watts at a few
tens of MHz. The only way to be sure is to make your own measurements.

	regards, tom
Article: 6679
Subject: Re: Power consumption (Xilinx FPGA) questions
From: "John Kramer" <schmupi@ostis.com>
Date: 13 Jun 1997 07:47:21 GMT
Links: << >>  << T >>  << A >>

How can the newsgroup predict:

1.  how much of the FPGA your circuit use? 
2.  the clock speed of your circuit?
3.  how much switching is happening on the circuit on the average?



Jacob W Janovetz <janovetz@coewl.cen.uiuc.edu> wrote in article
<5npvqo$5ne$1@vixen.cso.uiuc.edu>...
> Hello,
> 
>    I'm wondering if anyone has any 'standard' values for power
> consumption they use for Xilinx FPGAs.  The literature lists
> consumption on a per-CLB basis which varies depending on the
> programming.  However, mine are going into a reprogrammable
> system and I really can't predict that much, but would like
> near-maximum values for power supply consideration.  I'm 
> looking for the 4028XL-3, 4010XL-3, 4006E-4 specifically,
> but a general idea would serve me well, too.
> 
>     Thanks,
> 
>     Jake
> 
>  
> --
> janovetz@coewl.cen.uiuc.edu| Once you have flown, you will walk the earth
with
>    University of Illinois  | your eyes turned skyward, for there you have
been,
>                            | there you long to return.     -- da Vinci
>           PP-ASEL          | http://www.cen.uiuc.edu/~janovetz/index.html
> 
Article: 6680
Subject: Re: Altera Versus Xilinx
From: Stuart Wilson <stuartw@silicon.com.au>
Date: Fri, 13 Jun 1997 21:41:08 +1000
Links: << >>  << T >>  << A >>
Guys,

Take a look at the CompactPCI spec.

It enhances the PCI spec by specifying characteristic bus impedance to
be 65 ohm, and by insisting that each peripheral has 10 ohm stub
resistors, which reduce the effect of the capacitive load on the bus.

This appears to work very well and has been characterised using
simulation by core members of the PICMG CompactPCI group.

Stuart Wilson

Stuart Clubb wrote:
> 
> On Tue, 3 Jun 1997 22:33:13 GMT, jhallen@world.std.com (Joseph H
> Allen) wrote:
> 
> >Hey, don't have a cow man!  It's nothing that a few series resistors can't
> >fix.  They have to be large enough so that the input impedance with the
> >resistor would equal the reactance of a PCI single pin, but small enough so
> >that outputs can still drive the bus with enough current (assuming any
> >output pins are doubled up).  Around 10-27 ohms should work fine- make sure
> >there's no ground plane under the resistor (to reduce capacitance).
> 
> And this has been characterised and proven compliant?
> 
> I'm not "having a cow" as you so eloquently put it. It just concerns
> me that some engineers are reading, and swallowing, every piece of
> "marketing" seen on a web site or pdf file.
> 
> Marketing joke:
> A mathematician, an engineer, and an FPGA marketing VP are all asked
> how much two plus two is.
> 
> The mathemetician says "It is exactly four point zero."
> The engineer says "Four. Now can I have a pay rise?"
> The FPGA marketing VP says: "What do you want it to be?"
> 
> Stuart

-- 
Stuart Wilson
Silicon Consulting Services Pty Ltd
PO Box 82, Blackburn South
Victoria Australia
PH : +61 3 9877 9255
FX : +61 3 9877 9255

stuartw@silicon.com.au
Article: 6681
Subject: Re: Don't Design With Altera Parts... Altera Obsolete Parts
From: bowden@bark.nexen.com (Ray Bowden)
Date: 13 Jun 1997 13:40:35 -0400
Links: << >>  << T >>  << A >>
Yes, it is unfortunate that Altera has dropped this family.  However,
last year, Xilinx dropped their XC8XXX family with even less warning.
We found out about it by reading the EE Times.  I believe Altera has
always posted on their web site and in their newsletter on when they
were going to sunset parts.  They also indicate where you can buy
the old parts.  I believe the Altera EPX family was bought from
Intel, so I'm not surprised they would eventually drop it.

Xilinx, on the other hand, just dumped the XC8XXXX because they couldn't
program them with a high enough yield.

Ray Bowden

bowden@nexen.com

In article <33975456.F462CAC@aei-sandiego.com>,
robert bible  <robert@aei-sandiego.com> wrote:
>Everyone designing with FPGAs or CPLDs should stay away from altera if
>they expect a long product life for their design. I am sure that I am
>not the only person who is being burned by the discontinuing production
>of the EPX 880 EPX 8160... Altera is completely irresponsible shutting
>off production with minimal notice. What are we supposed to do. Redesign
>working items in production because Altera refuses to support their
>customers.
>
>Think about what life would be like if all the semiconductor companies
>acted like Altera.  I guess they do give EE job security. But I have
>better things to do than migrate designs from one device to another
>because of Altera marketing decisions.
>
>                        Robert Bible
>                        San Diego
>


-- 
Ray Bowden

bowden@nexen.com
Article: 6682
Subject: Verilog Simulation and Synthesis for FPGA Devices
From: hunterbp@magellan.Colorado.EDU (Brian P Hunter)
Date: 13 Jun 1997 19:53:33 GMT
Links: << >>  << T >>  << A >>
Hello all,

I'm looking for opinions (not sales pitches!) on some of the various
Verilog simulators and synthesis programs available today.  I'm looking for
a Windows 95 program that offers mixed-entry design methodology (schematics
and underlying verilog) and simulates and synthesizes primarily for Xilinx
and Altera devices.  A good schematic capture program, a nifty HDL editor,
project management--the works.  I want to see bells and whistles for my
money.  Synario seems to have what I'm looking for, but what experiences
have people had?

These are the vendors I'm looking at right now:
	Synario with FPGA Express
	VeriBest with FPGA Express (from right here in Boulder!)
	ViewLogic's ViewDraw, VCS, and FPGA Express

Can anyone here sway me in the right direction?  Thanks in advance!

Brian
Article: 6683
Subject: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
From: Karl Kristianson <KarlKristian@ntr.net>
Date: Fri, 13 Jun 1997 15:09:59 -0600
Links: << >>  << T >>  << A >>
FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!

Hello!

A new copy of Cadkey '97 is selling on the street for $1,195. To 
guarantee updates for the next year costs $350 more, bringing it up to 
$1,545 total!

We have available over 100 NEW copies of Cadkey 6.0 on CD for DOS in  
unopened, shrinkwrapped boxes with all manuals & documentation; which can 
be upgraded to Cadkey '97, INCLUDING the year's worth of free updates, 
for the street price of $595.

That's $950 LESS than the normal street price!

Or, maybe Cadkey 6.0 has enough power for you with no upgrade at all! 
(Cadkey '97 is basically Cadkey 8.0)

We're selling these for best offer, one or all, so please send your best 
offer on out to us!

If you would like more info on Cadkey 97, here's Cadkey 97's Web page: 
http://www.cadkey.com/cadkey/index.htm

Thanks!

Karl Kristianson
DreamQuest

Article: 6684
Subject: FPGA-like chip
From: ch794@freenet.buffalo.edu
Date: Fri, 13 Jun 1997 15:37:37 -0600
Links: << >>  << T >>  << A >>
Could anyone give me an opinion of the FPGA-like chip described at

http://www.geocities.com/SiliconValley/Pines/5297/short.html

It uses an array of FPGA-like processors that are much like FPGA's, but
use dynamic memory.

Packets of data move between them over a bus, each packet simulating a
simple microprocessor.

Your opinion would be greatly appreciated.

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6685
Subject: Re: Don't Design With Altera Parts... Altera Obsolete Parts
From: Ray Andraka <randraka@ids.net>
Date: Fri, 13 Jun 1997 18:10:02 -0400
Links: << >>  << T >>  << A >>
Ray Bowden wrote:
> 
> Yes, it is unfortunate that Altera has dropped this family.  However,
> last year, Xilinx dropped their XC8XXX family with even less warning.
> We found out about it by reading the EE Times.  I believe Altera has
> always posted on their web site and in their newsletter on when they
> were going to sunset parts.  They also indicate where you can buy
> the old parts.  I believe the Altera EPX family was bought from
> Intel, so I'm not surprised they would eventually drop it.
> 
> Xilinx, on the other hand, just dumped the XC8XXXX because they couldn't
> program them with a high enough yield.
> 


I think this was a special case for Xilinx.  As far as I know, the 8100
series was never formally introduced or made available to the general
public (other than for beta sites).  Xilinx has been very good about
sending notice well in advance of obsoleting production parts, and in
most cases there exists a reasonably easy path to a newer part.  It
would be great if other companies provided a fraction of the notice
Xilinx has been providing.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 6686
Subject: Re: Power consumption (Xilinx FPGA) questions
From: Ray Andraka <randraka@ids.net>
Date: Fri, 13 Jun 1997 18:13:34 -0400
Links: << >>  << T >>  << A >>
Jacob W Janovetz wrote:
> 
> Hello,
> 
>    I'm wondering if anyone has any 'standard' values for power
> consumption they use for Xilinx FPGAs.  The literature lists
> consumption on a per-CLB basis which varies depending on the
> programming.  However, mine are going into a reprogrammable
> system and I really can't predict that much, but would like
> near-maximum values for power supply consideration.  I'm
> looking for the 4028XL-3, 4010XL-3, 4006E-4 specifically,
> but a general idea would serve me well, too.
> 
>     Thanks,
> 
>     Jake

It really depends heavily on the number and frequency of nodes
switching.  For an absolute worst case you can use a large percentage of
nodes switching on every clock cycle (this normally won't happen except
in highly pipelined designs such as a bit serial processor).  Of course,
you also won't normally get very close to 100% utilization.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 6687
Subject: 100MHz SDRAMs with Xilinx?
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 13 Jun 1997 22:48:28 GMT
Links: << >>  << T >>  << A >>
I want to connect 4 SDRAMs (in a 2M x 32 configuration) to a XC40XXE in such
a way that I can do a full speed 100MHz continual write to the SDRAMs (reads
can be slow).  All signals will come from the fpga including data, address,
control and clock. All signals except clock will use the pad flip flops. 
Each data line originates from another fpga input pin, and goes through only
a single CLB (and it can use that CLB's flip flop as a pipeline register). 
The data rate and SDRAM clock will be 100MHz.  The SDRAMs are 3.3V parts and
the xilinx is 5V, but with TTL output levels.

Has anyone tried this?  Did it work?  100MHz seems fast for the control
logic, but no state machines actually have to go at that rate (only 50MHz or
maybe less).  The data paths do have to work though.

Does anyone know what the pad to pad skew is when the output flip-flops are
all driven from the same clock?  Anyone have any ideas on making the clock
driving the output pad flip flops available as an output pin at a low skew
compared to the clocked signals themselves?
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 6688
Subject: Re: Power consumption (Xilinx FPGA) questions
From: z80@dserve.com (Peter)
Date: Sat, 14 Jun 1997 11:54:17 GMT
Links: << >>  << T >>  << A >>

>How can the newsgroup predict:
>
>1.  how much of the FPGA your circuit use? 
>2.  the clock speed of your circuit?
>3.  how much switching is happening on the circuit on the average?

Quite right, but in fact it can be hard for the *designer* to know
this also.

I have spent a lot of time on dynamic Icc work, prototyping ASICs in
Xilinx FPGAs. One of the biggest problems is that the biggest single
factor in reducing dynamic Icc - clock gating - is very dodgy in
FPGAs. 


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 6689
Subject: Re: Verilog Simulation and Synthesis for FPGA Devices
From: gcardinali@iper.net (Giuliano Cardinali)
Date: Sat, 14 Jun 1997 12:20:10 GMT
Links: << >>  << T >>  << A >>
hunterbp@magellan.Colorado.EDU (Brian P Hunter) wrote:

I'm using QuickWorks 6.12 of QuickLogic Corp.. This is a very good
toolset that allows to entry your design in Verilog, VHDL, Boolean
Equations or Schematic. You can insert your design in mixed mode way.
However, the package works only with their very high speed
antifuse FPGA. The last release has very few bugs.

http:\\www.quicklogic.com

						Ciao!

Giuliano Cardinali
(consultant)

>Hello all,

>I'm looking for opinions (not sales pitches!) on some of the various
>Verilog simulators and synthesis programs available today.  I'm looking for
>a Windows 95 program that offers mixed-entry design methodology (schematics
>and underlying verilog) and simulates and synthesizes primarily for Xilinx
>and Altera devices.  A good schematic capture program, a nifty HDL editor,
>project management--the works.  I want to see bells and whistles for my
>money.  Synario seems to have what I'm looking for, but what experiences
>have people had?

>These are the vendors I'm looking at right now:
>	Synario with FPGA Express
>	VeriBest with FPGA Express (from right here in Boulder!)
>	ViewLogic's ViewDraw, VCS, and FPGA Express

>Can anyone here sway me in the right direction?  Thanks in advance!

>Brian


Article: 6690
Subject: Re: Don't Design With Altera Parts... Altera Obsolete Parts
From: "Steven Knapp" <sknapp @ optimagic.com>
Date: 14 Jun 1997 21:27:52 GMT
Links: << >>  << T >>  << A >>


William E. Lenihan III <lenihan3we@earthlink.net> wrote in article
<339B12C6.330A@earthlink.net>...
> robert bible wrote:
 
[snip]
> > I am sure that I am
> > not the only person who is being burned by the discontinuing production
> > of the EPX 880 EPX 8160... Altera is completely irresponsible shutting
> > off production with minimal notice. What are we supposed to do.
Redesign
> > working items in production because Altera refuses to support their
> > customers.
[snip]
> > 
> >                         Robert Bible
> >                         San Diego
> 
> Altera is really acting no differently than other semi makers. When
> demand falls, and technololgy becomes obsolete, they will shut down a
> product line. I think even Xilinx is starting to make noise about
> obsoleting some of their earlier chips. IC makers are getting more and
> more of their revenue from high volume products that have short
> production lives. That means those of us with longer-lived products have
> little choice but to invest in lifetime buys or plan for redesigns. You
> can make the redesign path easier by embracing synthesis and your HDL of
> choice.

From what I hear and can tell from various sources, Altera was in a bind
with the original foundry after acquiring Intel's PLD product line.  The
FX860 (or EX860) was a great little part but there was a lot of overlap
with Altera's  other product lines.  Having worked for a semiconductor
company in the past, believe me, they do not want to upset constomers by
discontinuing products.  However, it sometimes becomes necessary.  Ideally,
the vendor should provide some sort of an upgrade path or assistance during
the transition period.
> 
> In the past, Altera was guilty of not being vocal about their
> obsolescence plans, but they seemd to get better a year or two ago. The
> responsible thing to do would be for Altera (& other IC makers) to post
> this info on their web site, send mass mailing announcements to their
> customers, and even send press releases to the main Engineering
> magazines for inclusion in their "news & notes" sections. They should
> also be giving customers at least a 1 year transition zone before last
> buys. Has Altera failed to do these things in your case?
> =====================================================================
>  William Lenihan                            lenihan3we@earthlink.net
> 
>     "The greatest barrier to communication is the delusion that
>      it has already occurred."       -- Peter Cummings
> =====================================================================
> 
While they haven't sent out press releases on discontinued products, Xilinx
has been fairly responsible about customer notices.  I've seen various
mentioned in their XCELL newsletter (http://www.xilinx.com/xcell/xcell.htm)
and they do have a web site area dedicated to customer notifications
(http://www.xilinx.com/partinfo/notify/notify.htm) and discontinuances
(http://www.xilinx.com/partinfo/notify/mileston.htm).  In some cases,
Xilinx has worked with third-party supplies to provide "after-life"
product.

Altera also has a web site for customer notifications and product
discontinuance notices (http://www.altera.com/html/products/pcn.html).
-- 

Steven Knapp
OptiMagic Logic Design Solutions, Inc.
E-mail:  sknapp @ optimagic.com
Web:  http://www.optimagic.com
Article: 6691
Subject: Re: Don't Design With Altera Parts... Altera Obsolete Parts
From: johnm@Newbridge.COM (John McDougall)
Date: 15 Jun 1997 22:05:00 GMT
Links: << >>  << T >>  << A >>
Ya right. Xilinx has burned me. I had to respin a shit load of pcbs due to
xilinx discontinuing one of their 3064 packages. Actually it was a 3064A.

In article <01bc7923$1064f7c0$c149bacd@xilinx.com.xilinx.com>,
Steven Knapp <sknapp @ optimagic.com> wrote:
>
>
>William E. Lenihan III <lenihan3we@earthlink.net> wrote in article
><339B12C6.330A@earthlink.net>...
>> robert bible wrote:
> 
>[snip]
>> > I am sure that I am
>> > not the only person who is being burned by the discontinuing production
>> > of the EPX 880 EPX 8160... Altera is completely irresponsible shutting
>> > off production with minimal notice. What are we supposed to do.
>Redesign
>> > working items in production because Altera refuses to support their
>> > customers.
>[snip]
>> > 
>> >                         Robert Bible
>> >                         San Diego
>> 
>> Altera is really acting no differently than other semi makers. When
>> demand falls, and technololgy becomes obsolete, they will shut down a
>> product line. I think even Xilinx is starting to make noise about
>> obsoleting some of their earlier chips. IC makers are getting more and
>> more of their revenue from high volume products that have short
>> production lives. That means those of us with longer-lived products have
>> little choice but to invest in lifetime buys or plan for redesigns. You
>> can make the redesign path easier by embracing synthesis and your HDL of
>> choice.
>
>From what I hear and can tell from various sources, Altera was in a bind
>with the original foundry after acquiring Intel's PLD product line.  The
>FX860 (or EX860) was a great little part but there was a lot of overlap
>with Altera's  other product lines.  Having worked for a semiconductor
>company in the past, believe me, they do not want to upset constomers by
>discontinuing products.  However, it sometimes becomes necessary.  Ideally,
>the vendor should provide some sort of an upgrade path or assistance during
>the transition period.
>> 
>> In the past, Altera was guilty of not being vocal about their
>> obsolescence plans, but they seemd to get better a year or two ago. The
>> responsible thing to do would be for Altera (& other IC makers) to post
>> this info on their web site, send mass mailing announcements to their
>> customers, and even send press releases to the main Engineering
>> magazines for inclusion in their "news & notes" sections. They should
>> also be giving customers at least a 1 year transition zone before last
>> buys. Has Altera failed to do these things in your case?
>> =====================================================================
>>  William Lenihan                            lenihan3we@earthlink.net
>> 
>>     "The greatest barrier to communication is the delusion that
>>      it has already occurred."       -- Peter Cummings
>> =====================================================================
>> 
>While they haven't sent out press releases on discontinued products, Xilinx
>has been fairly responsible about customer notices.  I've seen various
>mentioned in their XCELL newsletter (http://www.xilinx.com/xcell/xcell.htm)
>and they do have a web site area dedicated to customer notifications
>(http://www.xilinx.com/partinfo/notify/notify.htm) and discontinuances
>(http://www.xilinx.com/partinfo/notify/mileston.htm).  In some cases,
>Xilinx has worked with third-party supplies to provide "after-life"
>product.
>
>Altera also has a web site for customer notifications and product
>discontinuance notices (http://www.altera.com/html/products/pcn.html).
>-- 
>
>Steven Knapp
>OptiMagic Logic Design Solutions, Inc.
>E-mail:  sknapp @ optimagic.com
>Web:  http://www.optimagic.com


Article: 6692
Subject: Re: Don't Design With Altera Parts... Altera Obsolete Parts
From: terry.harris@dial.pipex.com (Terry Harris)
Date: Sun, 15 Jun 1997 23:09:15 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <randraka@ids.net> wrote:

>I think this was a special case for Xilinx.  As far as I know, the 8100
>series was never formally introduced or made available to the general
>public (other than for beta sites). 

Make you wonder why there is 43 pages on the XC81xx series in the 96
data book, make me wonder if the XC95144 will ever be available. 

Cheers Terry...
Article: 6693
Subject: Re: ATMEL 17Cxxx ISP function ( no change of RESET/_OE )
From: Klaus_Leiss@ccl.lhag.de (Klaus-Guenter Leiss)
Date: 16 Jun 1997 09:31:14 GMT
Links: << >>  << T >>  << A >>
In article <339DB3E9.743A@informatik.uni-tuebingen.de>, 
dreher@informatik.uni-tuebingen.de says...


>I tried to change the polarity of the RESET/_OE pin to _RESET/OE
>("_" indicates active low) of the AT17C128 in the following manner
>(as described in the programming specification):
>

> ... code deleted


>but the polarity of pin RESET/_OE doesn't change.
>What's wrong?
>
>(I tried both RESET/_OE = 5V and =0V during steps 4 to 12).
>The routines generating the START and STOP bit and the adress/data
>bytes seem to work right; I have looked at the pins with a
>logic analyzer, and I can program the memory array.
>
>  Werner

Hello Werner,
did you power down your device before you tried the new polarity.
According to the programming specification you have to power it
down. My own observation confirms this.

Regards

Klaus

Article: 6694
Subject: San Diego, Ca.--MTS-FPGA Field Applications Engineer-Recruiter
From: amaraju@onramp.net (Executive Search)
Date: Mon, 16 Jun 1997 10:13:44 -0500
Links: << >>  << T >>  << A >>
Due to explosive growth in our FPGA product line, this Microelectronics
group of a $23billion Communications company is seeking a very talented
engineer for a MTS FPGA Field Applications Engineering position.

Location-San Diego,Ca.(Homebase) and part of the Southwest area.

Applicants should have at least 3 years exp in the design and development
of integrated circuits, either FPGA or ASIC. Expertise in VHDL or Verilog
HDL is required.

BSEE or MSEE required.
 
We are looking for a seasoned digital circuit designer with the
interpersonal skills to perform the presentation and customer relationship
roles.

Duties include:
Working with engineers to implement/optimize designs
Presentations to engineers and managers
Working with engineers to teach them tool flows
Educating customers on methods and techniques
Converting existing designs from competitors products to there FPGAs
Providing feedback for future products, features, and tools
Evaluting and prioritizing opportunities
Providing detailed technical info/assistance

FAE will be set up in a virtual office or will be located in leased
executive/shared office facilities.

Salary--$60-$90K base + 12 to 15% annual bonus and Field Sales Incentive
Plan(Normally a bonus of approximately 15 to 25/30% for design wins and
car allowance and who knows what else. 

THIS IS A VERY LUCRATIVE COMPENSATION PACKAGE FOR A TALENTED DESIGNER WHO
IS READY TO "COME OUT FROM BEHIND THE DESK".

THIS POSITION WON'T LAST LONG!!!

-- 
Eddie Amara- Executive Recruiter
SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" 
Home Page-http://www.spencersearch.com
Voice 972-378-0280
Fax 972-378-0279
Email amaraju@onramp.net
=====================================================================
Article: 6695
Subject: Help: Interfacing a Xilinx 4k to a microprocessor
From: Brian Heber <lnusdyt1.zzvczs@gmeds.com>
Date: Mon, 16 Jun 1997 09:45:43 -0700
Links: << >>  << T >>  << A >>
I'm trying to interface a TMS320C5x with a Xilinx 4k FPGA and
I'm looking for anyone who might have done something similar.
All I want to be able to do (at the moment) is to send a 16
bit message to the FPGA and/or read a 16 bit message from the
FPGA.

Does anyone have schematics and code on how to do this?  If
not, some other friendly advice would be greatly appreciated.

Thanks

Brian Heber
Article: 6696
Subject: PCMCIA CardBus controller...
From: "Austin Franklin" <dar5kroom@ix.netcom.com>
Date: 16 Jun 1997 18:23:15 GMT
Links: << >>  << T >>  << A >>
Hi,

Anyone know of a PCMCIA controller that does CardBus and is NOT a PCI
peripheral?

Thank you,

Austin Franklin
darkroom@ix.netcom.com

Article: 6697
Subject: Re: readback on xc40xx ?
From: "Dr. Endric Schubert" <endric@exemplar.com>
Date: Mon, 16 Jun 1997 13:45:06 -0700
Links: << >>  << T >>  << A >>
Werner Dreher wrote:
> 
... deleted
> 
> Greetings
>   Werner
> 
> ----------------------------------------------------------------
> Werner Dreher                 dreher@informatik.uni-tuebingen.de
> University of Tuebingen
> Technische Informatik / Computer Engineering
> Sand 13
> D-72076 Tuebingen, Germany


sososo Werner, im News trifft man sich wieder ;-)


-- 
-----------------------------------------------------------------------
Dr. Nils Endric Schubert                            endric@exemplar.com
Exemplar Logic
815 Atlantic Avenue, Suite 105
Alameda, CA 94501

Tel.: (510) 337 3761
Fax.: (510) 337 3799
-----------------------------------------------------------------------
Article: 6698
Subject: XCHECKER Download to Xilinx 9500 CPLDs
From: Simon Bacon <SimonBacon@nottile.demon.co.uk>
Date: Mon, 16 Jun 97 22:13:35 GMT
Links: << >>  << T >>  << A >>
Does anyone know how to use an XCHECKER cable to reliably download a
configuration to a Xilinx 9600 CPLD?

The Xilinx documentation is perfectly clear on how to do it, but
it doesn't work reliably, as Xilinx acknowledge.  Frequently, it
doesn't work at all.

Xilinx claim that the problem is:

  1. the XCHECKER cable contains an FPGA which is reloaded
     at the start of each configuration run.
  2. because of process enhancements in the FPGA part, the
     configuration no longer works properly unless you have
     an **old** XCHECKER.

I think that what they are saying is that their genius squad cannot
handle an XC3000 design.  Perhaps they should ask for some help from
Philip F., or one of the other regular posters to this newsgroup.

While I am on the subject (!), does anyone know why the (DOS) EZTAG
download program which drives the XCHECKER cable requires 16MB of
physical memory to download a JTAG stream.  Mere ineptness cannot be
enough; these guys must compete to get this good.

And yep, you are correct -- I am posting because Xilinx tech support
cannot or will not answer email.


Article: 6699
Subject: Re: XCHECKER Download to Xilinx 9500 CPLDs
From: Eric Ryherd <"vauto@tiac.net"@tiac.net>
Date: Mon, 16 Jun 1997 23:10:02 -0400
Links: << >>  << T >>  << A >>
Simon Bacon wrote:
> 
> Does anyone know how to use an XCHECKER cable to reliably download a
> configuration to a Xilinx 9600 CPLD?
> 
> The Xilinx documentation is perfectly clear on how to do it, but
> it doesn't work reliably, as Xilinx acknowledge.  Frequently, it
> doesn't work at all.
>snip<

We had a lot of problems donwloading to XC4000 parts.
Often we had to download 2 or 3 times and it would eventually
work (we sometimes had to power cyle too).
Never got an explanation from Xilinx but the newest
HardwareDebugger does seem to work quite reliably via
our sparc20 (we've been trying to get the PC version which is
much easier to connect to in our lab... but no luck so far...).
Documentation just didn't match the real product but we fumbled
around until we guessed at the right options. This was with the
"Beta pre-release" M1 release of the new tools based on NEOCAD.
We recently got a newer release but haven't loaded it yet (busy 
in the middle of a project).

-- 
Eric Ryherd            eric@vautomation.com
VAutomation Inc.       Synthesizable VHDL and Verilog Cores
20 Trafalgar Sq. #443  http://www.vautomation.com
Nashua NH 03063        (603) 882-2282  FAX:882-1587


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