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Messages from 6775

Article: 6775
Subject: Re: FPGA prototype board
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 26 Jun 1997 17:52:14 GMT
Links: << >>  << T >>  << A >>

Fliptronics (my business) will soon have available a prototyping board
with a large wire wrap prototyping area, a Xilinx XC4025E or XC4028EX,
upto 128 MB of DRAM, 128KB SRAM, and it plugs into a PC ISA slot. Viewlogic
schematics of example interfaces to the ISA bus, DRAM and SRAM will be 
included, as will be example software for talking to the board from the PC.
The Xilinx chip is easilly configured and reconfigured from the PC.

For more info please email me. fliptron@netcom.com

Philip Freidin



In article <5os2ed$kk6@hammerhead.dadd.ti.com> a840272@# Replace this line with your news domain (Steve Martindell) writes:
>I'm looking for a board that would have a Xilinx or Altera FPGA(either 
>soldered or socketed) with all the FPGA I/O pins brought out to a
>connector(s). A board like this would allow me to quickly protype 
>designs without having to send out to a board-shop. Does anyone 
>know of a company that makes a product like this?
>
>   thanks,
>          Steve Martindell
>          s-martindell@ti.com


Article: 6776
Subject: Re: Asynchronous Peripheral Download Mode, Probs
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 26 Jun 1997 11:57:23 -0700
Links: << >>  << T >>  << A >>
Erik Lins wrote:
> 
> 
> I have some trouble with that asynchronous peripheral mode. I can
> download the header and the first two frames, then within the third
> byte  of the next frame /INIT goes low -> frameerror, I think. That
> occurs always within the 74th byte transfer,


Erik, let me offer a few suggestions:

My first guess is that you are is writing data before the "memory clear"
is completed. If you only look at RDY/BUSY, you may be mislead by the
internally active pull-up resistor giving you a false RDY.
Try a 1K pull-down on RDY/BSY or watch for INIT to go high before you
start writiing.

Second suggestion:
Verify the preamble / length count sequence, appearing on DOUT at start.
This is our standard answer for anybody having configuration problems.
DOUT is the ideal pin to see whether the configuration process has
started properly.

Next guess:
Ringing on Write Strobe edges.

Last guess. 
Bit order of bytes is reversed, but you will see that easily on DOUT.

One comment: Different from what you might think and expect, CCLK does
NOT stop when a CRC error causes INITbar to go Low.

Peter Alfke
Xilinx Applications
Article: 6777
Subject: Re: FPGA prototype board
From: daveb@iinet.net.au (David R Brooks)
Date: Thu, 26 Jun 1997 23:39:35 GMT
Links: << >>  << T >>  << A >>
jhallen@world.std.com (Joseph H Allen) wrote:

:
:Should I use the 68 pin or 84 pin PLCC socket?
:How big should it be?
:
 84 PLCC, without a doubt. That's practically a "universal" Xilinx
socket, in that just about all sizes of part will fit. 68PLCC will
only seat the very small parts.

 See my web-page http://www.iinet.net.au/~daveb/tricks/ideas.html for
a way to remote-program XC4000 parts using the JTAG pins and a
parallel port.


--  Dave Brooks    <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
    "From" line rigged to foil spambots: daveb <at> iinet.net.au
Article: 6778
Subject: Re: FPGA prototype board
From: aaps@erols.com
Date: Thu, 26 Jun 1997 23:28:42 -0400
Links: << >>  << T >>  << A >>
Joseph H Allen wrote:
> 
> In article <5os7pl$247$1@vixen.cso.uiuc.edu>,
> Jacob W Janovetz <janovetz@coewl.cen.uiuc.edu> wrote:
> >a840272@# Replace this line with your news domain (Steve Martindell) writes:
> 
> >>I'm looking for a board that would have a Xilinx or Altera FPGA(either
> >>soldered or socketed) with all the FPGA I/O pins brought out to a
> >>connector(s). A board like this would allow me to quickly protype
> >>designs without having to send out to a board-shop. Does anyone
> >>know of a company that makes a product like this?
> 
> >   Both companies make evaluation boards for a limited number of their
> >devices.  Altera just started making one for educational use that has
> >a CPLD and one of their FLEX 10K devices on it.  I've seen it, but
> >haven't used it.  I have used the Xilinx ones, though.  They include
> >a download cable that attaches to a PC.
> 
> For a number of projects, I've hand wired boards which contain a PLCC Xilinx
> and a timer circuit which allows the it to configured over a serial cable.
> I've found this to be very useful: you first configure the Xilinx and then a
> UART in the configuration can communicate with the computer over the serial
> cable.  Of course the computer can be anything with an rs-232 port.
> 
> If there's interest, I'll run off a bunch of these off with a prototyping
> area. I would like to do it, but I want to be able to sell enough of them to
> pay the board house bill.  Basically, if I can sell at least 10 of them for
> $100 each I'll do it.
> 
> A few other features might be:
> 
>  - able to power the FPGA with rs-232 signal lines as well as external power
>    from a wall adaptor
>  - led which indicates that the configuration has occured
>  - can cause reconfiguration with change in DTR line status
>  - Xilinx pins are on an IDC connector, which can be used for jumpers or
>    cables as well as prototype wire-wraps.
>  - cheap FPGA included
>  - Socket for configuration prom and jumper option for master serial mode
>    configuration.
>  - Pads for a crystal and a socket for an oscillator can
> 
>  - I would include the board, software for PC and UNIX (including source) to
>    download the configuration data, and a UART example in OrCAD, ActiveCAD
>    and maybe Viewlogic formats (I have the OrCAD and Foundation devlopement
>    systems, and 45 runs of Viewlogic left on my key :-)
> 
> Should I use the 68 pin or 84 pin PLCC socket?
> How big should it be?
> 
> It would also be useful to make an ISA bus Xilinx prototype card, but that
> interests me less at the moment.
> --
> /*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}


Already been done. See http://www.erols.com/aaps
Article: 6779
Subject: PCI
From: dane@cnt.com (Daniel Elftmann)
Date: Fri, 27 Jun 1997 06:18:31 GMT
Links: << >>  << T >>  << A >>
Looking for any success/failures implementing Lucent and or Xilinx PCI Master. 
Please post or e-mail me dane@cnt.com
Article: 6780
Subject: Generating Sine/Cosine digitally
From: "Rune Bæverrud" <r@acte.no>
Date: Fri, 27 Jun 1997 09:32:41 +0200
Links: << >>  << T >>  << A >>
Hi All,

This is probably the simplest way possible you could make a Sine/Cosine
generator, and it is extremely appealing to a digital logic
implementation, because it only requires two adders!

This is how it works, you might have to dig into your old trigonometry
school books :)

1) SUPPOSE you had a cosine waveform.
2) Integrate it (an adder) - What do you get? A sine!
3) Integrate the sine (another adder) - What do you get? A cosine!
4) What happens if you feed 3) into 1)? You get an oscillator producing
   both the sine and cosine at the same time!

This is also one way you could implement an oscillator in the analog
world - by cascading two integrators and feed the output from the second
integrator into the input of the first one.

In the analog world, the oscillator would start because of some noise or
drifting in the op-amps used. The loop gain would have to be larger than
1 for the oscillator to reach full amplitude, with some
clipping/distortion as result.

In the digital world, there would be no signal noise, so the oscillator
would have to be started by preloading the integrators with a fixed
value.

NOTE: If the loop gain could be made to be exactly 1 - then there would
be no clipping/signal distortion!

Of course there are some coefficients to consider when integrating, but
the divide operations could be performed by looking only at the most
significant bits - a divide by 2^N requires ABSOLUTELY NO LOGIC!

Have a look at the pseudo code below for the implementation of this
algorithm, assuming both constants A and B are integers of value 2^N:

var SinReg, CosReg, tmp: Longint;
SinOut, CosOut: Output;
Constant A, B: Integer;

while (1) do begin
    tmp := SinReg;
    SinReg := SinReg + (CosReg div A);
    CosReg := CosReg + (tmp DIV -(A));

    SinOut := SinReg div B;
    CosOut := CosReg div B;
end;

This actually works, but the loop gain is >1 so it will start clipping
after oscillating for a while.

Now - I don't have the mathematical skills to produce a theory on this
principle, or choosing the right parameters for a really low distortion
oscillator. I was hoping that some of you out there would grab this
thing and improve the algorithm! This could be the perfect thing for
implementation in an FPGA/CPLD!

I have written a small program (an .EXE file) which you could download
to check out the algorithm. Source is included. This can be downloaded
from http://193.215.128.3/freecore

Regards,
Rune Baeverrud
Article: 6781
Subject: Re: Asynchronous Peripheral Download Mode, Probs
From: fliptron@netcom.com (Philip Freidin)
Date: Fri, 27 Jun 1997 08:38:39 GMT
Links: << >>  << T >>  << A >>
Eric, given that your chip is failing at other than a frame boundary 
suggests that there is something either wrong with the headder, or you 
are not loading bytes correctly. Check the DOUT pin on the device. You 
should see the same data as the header going into the chip, only bit 
serial. Since the length count is sent MSB first, this is a good place to 
make sure that you have not twisted the bytes around or something else silly.

Also, you need to make sure that you dont start sending data till 6uS after
the rising edge of init, which indicates the end of house cleaning. The last
sequence of house cleaning occurs after you take the prog pin high.


Steve,
	The 100K bytes per second is derived from the internal default 
serialization rate of about 1MHz. As you indicated, you can up this 
serial rate to 8MHz, which will then support a byte rate of about 1 MB 
per second. From this it can be seen that the parallel configuration 
modes are no faster than their underlying serial mode. This is because 
the only way out of the chips for daisy chain is serial, and this limits 
the frequency.

The minimum low time for the prog signal is documented on page 4-205 of 
the data book (9/96 vintage), and is > 300nS. I would recomend 1uS, just
to be safe.

Your software time out after release of prog is not needed. The chip 
indicates that it is ready for configuration by taking the init signal 
high, and the wait time is a function of the FPGA size (bigger chips take 
longer to finish housecleaning). This is also documented on the same page 
of the data book.

Of special note: Spec Ticck requires you to wait 5uS after Init goes high 
before starting the entertainment. I have debugged other peoples designs, 
where they had a high speed statemachine just waiting for the init going 
high, and the started configuration. The first few config bits were 
intermittently being ignored. Adding the delay fixed it. (This used to 
specced as 60nS in the data books of 5 years ago. guess who got them to 
change it.)

Hope that helps Steve.


Philip Freidin.



In article <33B122F4.7416@pa.msu.edu> Steve Gross <gross@pa.msu.edu> writes:
>Erik Lins wrote:
>> 
>> Hi everyone,
>> 
>> I have some trouble with that asynchronous peripheral mode. I can
>> download the header and the first two frames, then within the third
>> byte  of the next frame /INIT goes low -> frameerror, I think.
>
>From my experience with XC4ke parts, there are two things to worry
>about:
>
>1. Byte download rate.  Watch the RDY/BUSY line, which tells you
>   when byte "n" has been absorbed and the device is ready for
>   byte "n+1."  I have found the byte download rate to be rather
>   slow in these devices, down in the 100kBytes/second range.  
>   There is a CCLK speed bit which can be set in the bitstream
>   which should allow a higher byte download rate (for all bytes
>   *following* this bit...)
>
>   This is well documented in the Xilinx data books and I expect
>   it is not your problem.
>
>2. Timing of the PROG* pin.  There are 2 aspects of PROG* pin 
>   timing.  First, how long should the pin remain LOW?  Next, how
>   long after the rising edge of PROG* should one wait before writing
>   the first byte of the header?  Neither of these times are specified
>   in the Xilinx data book.  Worse, there is no handshaking to allow
>   the device to inform the "master" that it is OK to take PROG*
>   high or write the first byte of the header.  I had half expected
>   the RDY/BUSY line to tell me when it was OK to write the first 
>   byte of the header, but it doesn't.  
>
>   I have used software delays on the order of milliseconds to 
>   drive both of these times, following some trial-and-error
>   experimentation.
>
>   If I am wrong on the lack of specification or lack of handshaking
>   on this issue, I would be glad to be corrected!  
>
>Note that the only time INIT can go low is at a frame boundary.  If
>you see INIT going low at a point other than a frame boundary, start
>to suspect byte timing or PROG* timing.  
>
>Good luck.
>
>-Steve Gross


Article: 6782
Subject: Young cheerleader fucking and sucking cock
From: asdofjasd;ljf@;lkajdfa.s.com
Date: 27 Jun 1997 09:15:59 GMT
Links: << >>  << T >>  << A >>

Come visit the hottest new sex site on the internet Sexy-Girls  

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Article: 6783
Subject: Re: Verilog Simulation and Synthesis for FPGA Devices
From: Adrian Aichner <aichner@ecf.teradyne.com>
Date: 27 Jun 1997 12:48:20 +0200
Links: << >>  << T >>  << A >>
>>>>> "Giuliano" == Giuliano Cardinali <gcardinali@iper.net> writes:
    Giuliano> http:\\www.quicklogic.com

Make that
http://www.quicklogic.com
and it will work.
Article: 6784
Subject: Re: Generating Sine/Cosine digitally
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Fri, 27 Jun 1997 11:49:45 GMT
Links: << >>  << T >>  << A >>
"Rune Bæverrud" <r@acte.no> wrote:

>Hi All,
>
>This is probably the simplest way possible you could make a Sine/Cosine
>generator, and it is extremely appealing to a digital logic
>implementation, because it only requires two adders!
>
>This is how it works, you might have to dig into your old trigonometry
>school books :)
>

>Now - I don't have the mathematical skills to produce a theory on this
>principle, or choosing the right parameters for a really low distortion
>oscillator.

You don't have to. Just look up the papers by Volder in the 1950's, or
anything else on CORDIC (which can be used for more than just sines and
cosines). It's been re-invented often enough since.

- Brian

Article: 6785
Subject: Help!!
From: newsman@prl.research.philips.com (Usenet Admin)
Date: Fri, 27 Jun 1997 12:45:42 GMT
Links: << >>  << T >>  << A >>
Hi,
    Sorry to bother you all, does anyone know the URL for Philips low
power CPLD?
    I've tried to link to it through the Philips main home page, but the
semicondutor link seems to time out.

    Thanks in advance.

Christian Glover.

Article: 6786
Subject: Re: Generating Sine/Cosine digitally
From: Ray Andraka <randraka@ids.net>
Date: Fri, 27 Jun 1997 12:27:11 -0400
Links: << >>  << T >>  << A >>
Brian Drummond wrote:
> 
> "Rune Bæverrud" <r@acte.no> wrote:
> 
> >Hi All,
> >
> >This is probably the simplest way possible you could make a Sine/Cosine
> >generator, and it is extremely appealing to a digital logic
> >implementation, because it only requires two adders!
> >
> >This is how it works, you might have to dig into your old trigonometry
> >school books :)
> >
> 
> >Now - I don't have the mathematical skills to produce a theory on this
> >principle, or choosing the right parameters for a really low distortion
> >oscillator.
> 
> You don't have to. Just look up the papers by Volder in the 1950's, or
> anything else on CORDIC (which can be used for more than just sines and
> cosines). It's been re-invented often enough since.
> 
> - Brian
I've done a number of CORDIC designs in FPGAs, with some running at
better than 50MHz data rates.  I've used them for vector magnitude,
quadrature modulation and demodulation, root sum of squares combining,
simple sin/cos generation and log/exponent generation.  I've got one
paper on my website that discusses a high performance bit serial CORDIC
design (presented at design supercon '96), and another paper in the
works about CORDIC implementations in FPGAs.  THe smallest
implementation in that paper uses only 21 CLBs in a xilinx 4K part and
produces 16 bit results in about a microsecond and a half.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 6787
Subject: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 27 Jun 1997 10:40:38 -0700
Links: << >>  << T >>  << A >>
SALIX Technologies - Dan Simpkins wrote:
 
> Has anybody used Xilinx 3.3V XC4000XL devices in a mixed 5V/3V system?
> I am trying to find out if the "5V tolerant" I/O's on the XC4000XL
> devices can be driven from a low-impedance (i.e. CMOS) 5V source, or can only be driven from a higher-impedance TTL-style 5V source. 
> The published information from Xilinx has been changing as the parts
> have gone from lab to production.

Here comes the unambiguous answer from Xilinx Applications:

The Xilinx XC4000XL inputs are truly and unconditionally 5-V tolerant.
That means you can drive them from rail-to-rail 5-V CMOS outputs ( you
can even solder them directly to 5 V ) and have no measurable input
current, and no concerns about long-term reliability. 

I just finished writing a magazine article dealing with this subject,
and here is a short quote:

"Interfacing Between Devices with Different Supply Voltages 

Since all supply voltages share a common ground, there are no problems
interfacing logic Low levels in either direction. All potential problems
are in interfacing logic High levels.

5-V logic High driving 3.3 V input:
The highest 5-V output voltage must not force excessive current into the
3.3 V input.
Xilinx XC4000XL and XC5200XL pins have a circuit structure that
eliminates the classical clamp diode between pin and Vcc. The pin can
thus be driven as High as 5.5 V irrespective of the actual supply
voltage on the receiving input. These devices are, therefore,
unconditionally 5-V tolerant, and the user can ignore all interface
precautions. These devices achieve their excellent ESD protection (
several thousand volts ) by means of a patented diode-transistor
structure that does not rely on Vcc. "

end of quote.

This input structure also eliminates all concerns about power
sequencing:
If 5-V comes first, the inputs on XC4000XL tolerate this, even if their
own Vcc is still at zero.
If 3.3 V comes first, use the 5-V Vcc line as a global 3-state GTS (
active Low) input for the XC4000XL, it only costs you a pin. The
internal routing is for free.

This is the positive answer to your question. 
Now comes the apology:

During 1996, we investigated different solutions to this problem, and we
published information while these investigations and design activities
were still going on. That's what caused the confusion. It was a case of
too much information too early.

I am happy to report that we solved this ( admittedly knotty ) problem
in the best possible way for the user. You can intermix XC4000XL and
XC5200XL freely with 5-V logic, and you don't even have to worry about
power sequencing.

( Well, the 5-V inputs should have "TTL-like thresholds".)

I hope this clarifies the confusion.

Peter Alfke, Xilinx Applications
Article: 6788
Subject: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
From: Phil Short <pjs3@ix.netcom.com>
Date: Fri, 27 Jun 1997 11:45:34 -0700
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> SALIX Technologies - Dan Simpkins wrote:
> 
[snip]
> 5-V logic High driving 3.3 V input:
> The highest 5-V output voltage must not force excessive current into the
> 3.3 V input.
> Xilinx XC4000XL and XC5200XL pins have a circuit structure that
> eliminates the classical clamp diode between pin and Vcc. The pin can
> thus be driven as High as 5.5 V irrespective of the actual supply
> voltage on the receiving input. These devices are, therefore,

So, if I have a 5V supply running 10% high, will I have to worry
about overshoot on CMOS outputs (due to 'transmission-line'
effects on high-slew-rate signals) driven from the 5.5V supply?

> unconditionally 5-V tolerant, and the user can ignore all interface
> precautions. These devices achieve their excellent ESD protection (
> several thousand volts ) by means of a patented diode-transistor
> structure that does not rely on Vcc. "
> 
> end of quote.
> 
> This input structure also eliminates all concerns about power
> sequencing:
> If 5-V comes first, the inputs on XC4000XL tolerate this, even if their
> own Vcc is still at zero.
> If 3.3 V comes first, use the 5-V Vcc line as a global 3-state GTS (
> active Low) input for the XC4000XL, it only costs you a pin. The
> internal routing is for free.
> 
> This is the positive answer to your question.
[snip]
> 
> I hope this clarifies the confusion.
> 
> Peter Alfke, Xilinx Applications

Phil
Article: 6789
Subject: Re: XCHECKER Download to Xilinx 9500 CPLDs
From: Daniel Jones <dmjones@ix.netcom.com>
Date: Fri, 27 Jun 1997 18:53:05 GMT
Links: << >>  << T >>  << A >>
In article <33A7160F.2C53@nospam.berlin.snafu.de>,
	Gerhard Hoffmann <ghf@nospam.berlin.snafu.de> wrote:
>Eric Ryherd wrote:
>
>> We had a lot of problems donwloading to XC4000 parts.
>> Often we had to download 2 or 3 times and it would eventually
>> work (we sometimes had to power cyle too).
>> Never got an explanation from Xilinx but the newest
>> HardwareDebugger does seem to work quite reliably via
>
>I second that. I think that Xcheckers can have LatchUp effects
>if you don't apply power to your prototype before turning
>on your pc. Sometimes there are situations where it simply
>does not work. I found that it then draws more current ( i 
>remember something like an extra 150 mA ) and heats up a bit. 
>
>My whole population of 3 Xcheckers shows this behaviour. It
>seems to depend somewhat on the RS232 port.
>
>Since i don't want to power down my pc whenever i play with
>the prototype, i now use my own download program and the
>printer port.
>
>So, if you have Xchecker trouble, try the proper 
>power up sequence. Maybe it helps.
>
I want to exlicitly thank you guys for discussing this issue. 
I now know that latchup in the Xchecker was the cause of all of
my intermittant initialization problems. My new drill is to 
disconnect the Xchecker from the target whenever power is cycled.
Life is good again.

Dan

Article: 6790
Subject: Re: FPGA prototype board
From: Steve Casselman <sc@vcc.com>
Date: Sat, 28 Jun 1997 01:49:28 GMT
Links: << >>  << T >>  << A >>
Steve Martindell wrote:
> 
> I'm looking for a board that would have a Xilinx or Altera FPGA(either
> soldered or socketed) with all the FPGA I/O pins brought out to a
> connector(s). A board like this would allow me to quickly protype
> designs without having to send out to a board-shop. Does anyone
> know of a company that makes a product like this?
> 
>    thanks,
>           Steve Martindell
>           s-martindell@ti.com
Of course there is alwasy Virtual Computer. The hot works
board will soon have a prototype daughter card.
checkout http://www.vcc.com/products/pci6200.html
The base card is $995 (comes with lots of software)
Proto Card $199.
-- 
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com
Article: 6791
Subject: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
From: Tom Burgess <Tom_Burgess@bc.sympatico.ca>
Date: Sat, 28 Jun 1997 01:39:21 -0700
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> <excerpt>
> Xilinx XC4000XL and XC5200XL pins have a circuit structure that
> eliminates the classical clamp diode between pin and Vcc. The pin can
> thus be driven as High as 5.5 V irrespective of the actual supply
> voltage on the receiving input. These devices are, therefore,
> unconditionally 5-V tolerant, and the user can ignore all interface
> precautions. These devices achieve their excellent ESD protection (
> several thousand volts ) by means of a patented diode-transistor
> structure that does not rely on Vcc. "

Just curious about the mental model I should use here. Is it like a
5.5V "superZener", or something less fixed & abrupt? I'm wondering, too,
about the clamping effect on overshoots. Is a Spice model available?
The relevant patent number would also be helpful. This certainly
sounds like the way 3V input protection should work, and I congratulate
Xilinx for doing the right thing on this. Power sequencing requirements 
would have been a total nightmare.

	regards, tom
	tburgess@drao.nrc.ca
Article: 6792
Subject: Verilog Simulation and Synthesis for FPGA Devices
From: "Robert M. Münch" <Robert.M.Muench@SCRAP.de>
Date: Sat, 28 Jun 1997 10:39:48 +0200
Links: << >>  << T >>  << A >>
> -----Original Message-----
> From:	hunterbp@magellan.Colorado.EDU (Brian P Hunter)
> [SMTP:hunterbp@magellan.Colorado.EDU]
> Posted At:	Friday, June 13, 1997 9:54 PM
> Posted To:	fpga
> Conversation:	Verilog Simulation and Synthesis for FPGA Devices
> Subject:	Verilog Simulation and Synthesis for FPGA Devices
> 
> These are the vendors I'm looking at right now:
> 	Synario with FPGA Express
> 	VeriBest with FPGA Express (from right here in Boulder!)
> 	ViewLogic's ViewDraw, VCS, and FPGA Express
> 
> Can anyone here sway me in the right direction?  Thanks in advance!
> 
> 
[Robert M. Münch]  Yes, don't use Veribest! Their programs are a
collection of bugs! Nothing works! We tried the synthesis and their
optimizer is real good -> you won't get any signal in the result if you
are lucky and the program doens't crash your machine! Try Synopsis FPGA
Express and VCS.

Robert M. Muench
SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany

==> Private mail : r.m.muench@ieee.org <==
==>            ask for PGP public-key            <==


Article: 6793
Subject: Re: Help!!
From: Tom Burgess <Tom_Burgess@bc.sympatico.ca>
Date: Sat, 28 Jun 1997 01:48:55 -0700
Links: << >>  << T >>  << A >>
Usenet Admin wrote:
> 
> Hi,
>     Sorry to bother you all, does anyone know the URL for Philips low
> power CPLD?
>     I've tried to link to it through the Philips main home page, but the
> semicondutor link seems to time out.
> 
>     Thanks in advance.
> 
> Christian Glover.

I assume you are referring to the excellent:

http://www.coolpld.com/

Last time I checked, the main Philips page seemed pretty useless.

	regards, tom
Article: 6794
Subject: Programming Xilinx 3k/4k in C ?
From: z80@dserve.com (Peter)
Date: Sat, 28 Jun 1997 08:51:41 GMT
Links: << >>  << T >>  << A >>

Just read in one of UK's electronics rags that a UK firm has developed
a C compiler.

Sounds great!

There was no other info, like e.g. if it outputs XNF, or the bitstream
directly. In the latter case, it will probably cost a fortune...


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 6795
Subject: Re: Help!!
From: Roger <roger@solaris.x86.org>
Date: Sat, 28 Jun 1997 17:17:47 +0800
Links: << >>  << T >>  << A >>
Usenet Admin wrote:
> 
> Hi,
>     Sorry to bother you all, does anyone know the URL for Philips low
> power CPLD?
>     I've tried to link to it through the Philips main home page, but the
> semicondutor link seems to time out.
> 
>     Thanks in advance.
> 
> Christian Glover.

http://www.coolpld.com

Yau Man Wai , Roger ICQ UIN: 703065
Department of Electronic Engineering HD2
The Hong Kong Polytechnic University
http://www.net.polyu.edu.hk/~rogeryau
Article: 6796
Subject: Smart Card Design and Interface. How?
From: hellotwt@twt.aust.com (TJ)
Date: Sat, 28 Jun 1997 09:48:17 GMT
Links: << >>  << T >>  << A >>
I would like to implement a security entry/logging functions using
smart cards or any other memory cards. I would also like to design the
reader using microcontroller.
Are these cards expensive? Can I get them in Australia? Do Smart Card
manufacturers publish data sheets on how to interface them?

THANKS IN ADAVANCE


Article: 6797
Subject: Re: Any designs to avoid in FPGAs
From: z80@dserve.com (Peter)
Date: Sat, 28 Jun 1997 10:15:42 GMT
Links: << >>  << T >>  << A >>

I would also add that one should avoid doing low-power designs, i.e.
ones where one is gating clocks to parts of the circuit to reduce
dynamic Icc.

With the older XC3000 parts one could do this OK, just by assigning
e.g. a long-line to the clock. But the present-day versions are not
only much faster but also have a different distribution of delays
within the device, and this just does not work.

I have concluded that the only way is what Xilinx nowadays recommend,
i.e. use the global clock for *every* D-type, and use clock-enables.
But this makes it draw a lot of current than would be the case
otherwise.


Article: 6798
Subject: Re: Smart Card Design and Interface. How?
From: peb@transcontech.co.uk ("Paul E. Bennett")
Date: Sat, 28 Jun 97 11:45:18 GMT
Links: << >>  << T >>  << A >>
In article <33b7dcd4.6054265@news.idx.com.au> hellotwt@twt.aust.com "TJ" writes:

> I would like to implement a security entry/logging functions using
> smart cards or any other memory cards. I would also like to design the
> reader using microcontroller.
> Are these cards expensive? Can I get them in Australia? Do Smart Card
> manufacturers publish data sheets on how to interface them?

Expense depends on facility
The main players can supply globally
Yes, there are application notes and data sheets for interfacing. Many 
smart card facilities are made for embedding in a product.

When I get to my info again I could post some contacts (if I remember).

-- 
Paul E. Bennett ................... <peb@transcontech.co.uk>
Transport Control Technology Ltd.   <http://www.tcontec.demon.co.uk/>
+44 (0)117-9499861                  <enquiry@transcontech.co.uk>
Going Forth Safely

Article: 6799
Subject: Re: Smart Card Design and Interface. How?
From: Andrew DeWeerd <deweerd@mindspring.com>
Date: Sat, 28 Jun 1997 08:51:37 -0400
Links: << >>  << T >>  << A >>
TJ wrote:
> 
> I would like to implement a security entry/logging functions using
> smart cards or any other memory cards. I would also like to design the
> reader using microcontroller.
> Are these cards expensive? Can I get them in Australia? Do Smart Card
> manufacturers publish data sheets on how to interface them?
> 
> THANKS IN ADAVANCE


I built automotive electronics to read and write to a smartcard.  It was
not especially difficult, but I did need to sign a non-disclosure
agreement with the card company (Schlumberger) before they would send me
the documentation for the card.  I used a PIC16C63 in that design, but
you could use ANY device for this purpose.

There are many different types of smartcards.  Each offers options in
their communcations, memory, security features, etc.  Talk to
Schlumberger (France-based) or Gemplus (???-based).

Andrew DeWeerd


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