Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 20250

Article: 20250
Subject: Re: Count 1's algorithm...
From: Nick Macias <nmacias@cellmatrix.com>
Date: Wed, 02 Feb 2000 11:04:52 -0700
Links: << >>  << T >>  << A >>
The brute force way (simplest design perhaps) would be to build an 8-bit
lookup table, and just record the number of ones for each entry
(0-255)..so it would be a 256x8 ROM. Use it 3 times for 1 24-bit
word...Pretty fast too.
Article: 20251
Subject: Re: XC9536 and Abel
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Wed, 2 Feb 2000 11:37:07 -0700
Links: << >>  << T >>  << A >>
Björn Lindegren wrote in message
<7qYl4.4016$jg4.8056@nntpserver.swip.net>...
>Hi.
>Using Xilinx Foundation series 2.1i, and I want to build a program with
tree
>states to XC9536 in the programming language Abel via State Editor.
>
>In state number one outport q1 activates and all the others are
deactivated.
>In state no two outport q2 activate and q1, q2 is activated and in the last
>state is only q3 activated.
>
>When I program XC9536 with the code in the end of this message, all
outports
>(q1, q2, q3) are activated.
>
>What's wrong?
>
>Thankful for help
>
>Björn Lindegren
>"
>"  File: E:\PROGRAM\XFS2.1\ACTIVE\PROJECTS\95360130\delay.abl
>"  created: 02/02/00 16:31:30
>"  from: 'E:\PROGRAM\XFS2.1\ACTIVE\PROJECTS\95360130\delay.asf'
>"  by:  fsm2hdl - version: 2.0.1.53
>"
>module delay
>Title 'delay'
>
>Declarations
>
>"clocks
>CLK PIN 43;
>
>"input ports
>
>"output ports
>q1 PIN 22;
>q2 PIN 21;
>q3 PIN 13;
>
>"******** SYMBOLIC state machine: Sreg0 ******
>Sreg0 STATE_REGISTER;
>S1, S2, S3 STATE;
>
>
>"diagram ACTIONS
>
>"************* state machine: Sreg0 *************
>
>Equations
>" clock signals definitions
> Sreg0.clk = CLK;
>
>State_diagram Sreg0
>
>
>State S1:
>
>    q1=1;
>    q2=0;
>    q3=0;
>    x=x+1;
>     IF ('x<1000') THEN
>    S1
>     ELSE  IF ('x=1000') THEN
>        S2;
>
>
>State S2:
>
>    q1=0;
>    q2=1;
>    q3=0;
>    x=x+1;
>     IF ('x<2000') THEN
>    S2
>     ELSE  IF ('x=2000') THEN
>        S3;
>
>
>State S3:
>
>    q1=0;
>    q2=0;
>    q3=1;
>    x=x+1;
>     IF ('x<3000') THEN
>    S3
>     ELSE  IF ('x=3000') THEN
>        S1 WITH
>     x=1;
>     ENDWITH;
>
>" end of state machine - Sreg0
>
>
>end delay


You don't have a reset state or a default state.  Sreg starts up in an
unknown state and can't transition to a known state.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

Spelling Counts!  You don't loose your money - you lose it.



Article: 20252
Subject: Re: XC9536 and Abel
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 02 Feb 2000 14:05:55 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------D49C00D5DF504C438744CE85
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

"Björn Lindegren" wrote:

> Hi.
> Using Xilinx Foundation series 2.1i, and I want to build a program with tree
> states to XC9536 in the programming language Abel via State Editor.
>
> In state number one outport q1 activates and all the others are deactivated.
> In state no two outport q2 activate and q1, q2 is activated and in the last
> state is only q3 activated.
>
> When I program XC9536 with the code in the end of this message, all outports
> (q1, q2, q3) are activated.
>
> What's wrong?

In earlier versions of the State editor (in Foundation 1.5), I noticed a similar problem.  Outputs would not work correctly if you used vector equations such as "q = ^b010".  You had to explicitly split-up the equation into three equations: "q0=0; q1=1; q2=0;" and attach those to the output states.  Then the resulting design would work.

--------------D49C00D5DF504C438744CE85
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------D49C00D5DF504C438744CE85--

Article: 20253
Subject: Re: Virtex DLL inoperability
From: winzker@aol.com (Winzker)
Date: 02 Feb 2000 19:30:40 GMT
Links: << >>  << T >>  << A >>
Steve, do you have the latest Service Pack (which is SP4).

Xilinx had a DLL problem in Service Pack 3 (or 2? I dont recall).

Marco

----------------------------------------------------------------------------
Marco Winzker
Liesegang electronics
(as always, speaking only for myself)

Article: 20254
Subject: Re: Count 1's algorithm...
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 02 Feb 2000 12:04:14 -0800
Links: << >>  << T >>  << A >>
If you want to go real "brute force" and fast, use the Virtex or Virtex-E
BlockRAM with two levels:

First level four 4k x 1 BlockRAMs. They are dual-ported, so each can look
at 12 inputs on one port, plus the other 12 inputs on the other port, each
port generating 1 output per BlockRAM, for a total of 8 outputs. ( The
look-up code is the same for both ports !)
Second level: 256 x 16, converting the 8 signals into the appropriate code,
could of course be only 5 bits.
BlockRAM has synchronous read, so you have one extra clock period of
latency, but the clock could run at over 150 MHz.
If you don't like the latency, build the 4-bit adder in CLBs.

The "price" of BlockRAMs is a bit strange: If you have barely enough, any
additional BlockRAM would be very expensive. If you don't use them all, the
remaining BlockRAMs are free, and they can be used ( or abused ) as shown
above.

Peter Alfke, Xilinx Applications
=======================

Nick Macias wrote:

> The brute force way (simplest design perhaps) would be to build an 8-bit
> lookup table, and just record the number of ones for each entry
> (0-255)..so it would be a 256x8 ROM. Use it 3 times for 1 24-bit
> word...Pretty fast too.

Article: 20255
Subject: Re: Spartan II availability and pricing
From: ldoolitt@recycle (Larry Doolittle)
Date: 2 Feb 2000 20:16:04 GMT
Links: << >>  << T >>  << A >>
Tom Burgess (tom.burgess@hia.nrc.ca) wrote:
: EDN mag, Jan 6th issue, p. 24 had some unattributed
: Spartan-2 price projections:
                  ^^^^^^^^^^^
: XC2S15 3.95, XC2S30 4.95, XC2S50 7.95, XC2S100 9.95, XC2S150 12.95
: The fine print states that this pricing is for 250,000 units, lowest
: speed and cheapest package, end of 2000. They'll be throwing in a free
: pizza and beverage with every million-dollar order, too :)

Thanks.  And I guess I shouldn't have been fooled into thinking
that production in 1Q00 meant anything sooner than March 31.
My guesses for small quantity prices at that time stands.  As
someone pointed out, the first price break comes at 25 (for
Spartan, at least), and counts for a good 10-20%.

I put up a web page to make searches for _real_ P&A easier:
   http://recycle.lbl.gov/xc2search.html
Still nothing :-(

     - Larry Doolittle  <LRDoolittle@lbl.gov>
Article: 20256
Subject: Foundation
From: "Veselic Mladen" <veselic@eunet.yu>
Date: Wed, 2 Feb 2000 22:37:22 +0100
Links: << >>  << T >>  << A >>
Hello,

Is there a way to download a Foundation software for free somewhere?
Because I am from Serbia there is no way to pay for it.
If anybody have it and want to send me somehow please notify me by email.
I have 3 Xilinx devices but I can't configure them.

I would be grateful if someone help me.

veselic@eunet.yu

Veselic Mladen


Article: 20257
Subject: Visualizing EDIF netlist for Xilinx
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Wed, 02 Feb 2000 22:18:17 GMT
Links: << >>  << T >>  << A >>
Hi,

I have recently started working with Xilinx Foundation tools and I am still
on the learning curve with VHDL. My previous experience is AHDL for Altera.

I am having troubles understanding what synthesis does with the code I write
so I would like to be able to see it somehow in the schematic or similar
format. I know that Sinplify has this option but I am not going to have it
in the hear future. Is there any way to do this apart from manual
reconstructing schematics from the EDIF netlist?

I will appreciate any input on this matter. Thanks.

Mikhail Matusov



Article: 20258
Subject: Can hobbyist buy altera in uk?
From: "funky jim" <jmc8197@hotmail.com>
Date: Wed, 2 Feb 2000 23:37:07 -0000
Links: << >>  << T >>  << A >>
Does any place in the UK sell Altera devices to the hobbyist.


Article: 20259
Subject: Re: Foundation
From: "funky jim" <jmc8197@hotmail.com>
Date: Wed, 2 Feb 2000 23:46:33 -0000
Links: << >>  << T >>  << A >>

Are you Serbian?
If yes, have you been a naughty boy?
If yes, then no.

Veselic Mladen <veselic@eunet.yu> wrote in message
news:87a83l$2k$1@SOLAIR2.EUnet.yu...
> Hello,
>
> Is there a way to download a Foundation software for free somewhere?
> Because I am from Serbia there is no way to pay for it.
> If anybody have it and want to send me somehow please notify me by email.
> I have 3 Xilinx devices but I can't configure them.
>
> I would be grateful if someone help me.
>
> veselic@eunet.yu
>
> Veselic Mladen
>
>


Article: 20260
Subject: Re: part time
From: "funky jim" <jmc8197@hotmail.com>
Date: Wed, 2 Feb 2000 23:50:53 -0000
Links: << >>  << T >>  << A >>
geesh!
Us poor sods have to work full time. You youngsters don't know wot hardwork
is.

Jamil Khaib <Khatib@ieee.org> wrote in message
news:3896CE3C.96E675E0@ieee.org...
> Hi
> is there any part time job that I can do via the internet
>
> I know VHDL and FPGA design and basics of verifications
>
> Thanks
>


Article: 20261
Subject: Looking for a small, fast CPU core for FPGA
From: Irit <irit@cmt.co.il>
Date: Thu, 03 Feb 2000 03:12:38 +0200
Links: << >>  << T >>  << A >>
Hello,
I am looking for a CPU core which can be placed in an FPGA. It should
have the following features:

1. 32-bit registers and ALU, integer only; don't need multiply or
divide.

2. Fast enough to run at 66 MHz on a Virtex or Apex FPGA.

3. Not too big (a single instance should fit in less than 100K system
gates, whatever it means).

4. Possible to have more than one instance in a single chip; not locked
to specific cells or I/O pins.

5. Must have code development tools (assembler, linker, debugger)
available; C compiler is nice-to-have but not mandatory.

6. Preferably synthesizable VHDL or Verilog; if available as netlist or
routed block, must have a VHDL simulation model.

7. Can be converted later to an ASIC cell.

I would greatly appreciate any pointers; after all replies (if any) have
been sent, I will post a summary in the relevant NGs.

Please send replies to my email (assaf_sarfati@yahoo.com) as well as
posting them; I suspect my NG server either loses posts or deletes them
after a few minutes.

               Thanks in Advance
               Assaf Sarfati


Article: 20262
Subject: Re: Can hobbyist buy altera in uk?
From: Tim Tyler <tt@cryogen.com>
Date: Thu, 3 Feb 2000 02:22:56 GMT
Links: << >>  << T >>  << A >>
funky jim <jmc8197@hotmail.com> wrote:

: Does any place in the UK sell Altera devices to the hobbyist.

To quote from http://ftp.altera.com/html/office.6.html

UNITED KINGDOM:

Ambar-Cascom, Ltd.
The Gatehouse
Gatehouse Way
Aylesbury, Buckinghamshire
HP19 3DL
United Kingdom

Flexible Logic (Arrow)
St.Martins Business Centre
Cambridge Road
Bedford
MK42 0LF
United Kingdom

Thame Components, Ltd.
Thame Park Road
Thame
Oxfordshire
OX9 3UQ
United Kingdom
URL: http://www.tcl.memec.com/

[I snipped out phone numbers and email addresses so I'm less responsible
for any spam these folks get.  See the original page for these.]

The URL at the end has lots of Altera bits and pieces - but they don't
seem to be stuck together very much.

http://www.computer-solutions.co.uk/ also have Altera parts, I believe.

This information is probably of low quality - but it's the best I can
manage :-|
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

Never attempt to replicate a successful experiment.
Article: 20263
Subject: Re: Announcement: Xilinx on Linux HowTo
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Wed, 02 Feb 2000 21:46:45 -0500
Links: << >>  << T >>  << A >>
The only Windows calls that are being translated are some file IO at the beginning and end of each program, 99.9999% of the time
is spent running straight C code with no OS calls. There shouldn't be any performance difference at all.

Josh

eml@riverside-machines.com.NOSPAM wrote:
> 
> On Sun, 30 Jan 2000 20:06:15 -0500, "B. Joshua Rosen"
> <bjrosen@polybus.com> wrote:
> 
> >I've just put up a HowTo page for running Xilinx place and route tools under Linux.
> >
> >http://www.polybus.com/xilinx_on_linux.html
> 
> Very nice work, but what about the overhead of running the windows
> emulator? Is this significant?
> 
> Thanks
> 
> Evan
Article: 20264
Subject: Re: part time
From: "Matt Billenstein" <mbillens@one.net>
Date: Thu, 03 Feb 2000 05:28:13 GMT
Links: << >>  << T >>  << A >>
Uh, sign me up too...  I've got time, tools, and smarts.

m


Matt Billenstein
http://w3.one.net/~mbillens/
mbillens@one.net


"Jamil Khaib" <Khatib@ieee.org> wrote in message
news:3896CE3C.96E675E0@ieee.org...
| Hi
| is there any part time job that I can do via the internet
|
| I know VHDL and FPGA design and basics of verifications
|
| Thanks
|


Article: 20265
Subject: Re: Visualizing EDIF netlist for Xilinx
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Thu, 03 Feb 2000 05:48:54 GMT
Links: << >>  << T >>  << A >>
On Wed, 02 Feb 2000 22:18:17 GMT, "Mikhail Matusov"
<matusov@ANNTIsquarepegSPPAMM.ca> wrote:

>Hi,
>
>I have recently started working with Xilinx Foundation tools and I am still
>on the learning curve with VHDL. My previous experience is AHDL for Altera.
>
>I am having troubles understanding what synthesis does with the code I write
>so I would like to be able to see it somehow in the schematic or similar
>format. I know that Sinplify has this option but I am not going to have it
>in the hear future. Is there any way to do this apart from manual
>reconstructing schematics from the EDIF netlist?
>
>I will appreciate any input on this matter. Thanks.
>
>Mikhail Matusov

Any reason why you can't get an evaluation copy of synplify?
The guy sitting at the desk next to mine just got one, and seems quite
impressed by the schematic viewer.

Regards,
Allan.
Article: 20266
Subject: Re: Count 1's algorithm...
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 03 Feb 2000 07:01:51 GMT
Links: << >>  << T >>  << A >>
I played around, and got this 24-bit design down to three BlockRAMs plus one
CLB, in Virtex or Spartan-II.

The design can be clocked at >150 MHz. It uses the first clock edge to clock
in the 24 bits of data, then uses the next clock to generate the binary
result, i.e it is pipelined and thus can generate a new result every clock.

Here are the details:

Use 22 bits to dual-port address two 2k x 2 BlockRAMs. Each BlockRAM has two
outputs per port, for a total of eight outputs, in two sets of 4-bit
binary-weighted signals. Remember that the BlockRAM, used as a ROM here,
is a
clocked device.

Feed the remaining two input bits to one LUTs, generating only the sum (ignore
the carry).

Use the 8 BlockRAM outputs and the two remaining inputs to address one
1k x 4
BlockRAM which generates the 4 MSBs of the 5-bit result.

Generate the LSB of the result in one 3-input LUT, in parallel with the
BlockRAM.

All LUTs have their own pipelining flip-flop "for free".

Not too expensive and very fast, if you can tolerate the pipelining.

Thanks for the brain-stretcher !

Peter Alfke, Xilinx Applications





Peter Alfke wrote:

> If you want to go real "brute force" and fast, use the Virtex or Virtex-E
> BlockRAM with two levels:
>
> First level four 4k x 1 BlockRAMs. They are dual-ported, so each can look
> at 12 inputs on one port, plus the other 12 inputs on the other port, each
> port generating 1 output per BlockRAM, for a total of 8 outputs. ( The
> look-up code is the same for both ports !)
> Second level: 256 x 16, converting the 8 signals into the appropriate code,
> could of course be only 5 bits.
> BlockRAM has synchronous read, so you have one extra clock period of
> latency, but the clock could run at over 150 MHz.
> If you don't like the latency, build the 4-bit adder in CLBs.
>
> The "price" of BlockRAMs is a bit strange: If you have barely enough, any
> additional BlockRAM would be very expensive. If you don't use them all, the
> remaining BlockRAMs are free, and they can be used ( or abused ) as shown
> above.
>
> Peter Alfke, Xilinx Applications
> =======================
>
> Nick Macias wrote:
>
> > The brute force way (simplest design perhaps) would be to build an 8-bit
> > lookup table, and just record the number of ones for each entry
> > (0-255)..so it would be a 256x8 ROM. Use it 3 times for 1 24-bit
> > word...Pretty fast too.
Article: 20267
Subject: Crossing clock domain boundaries in digital ASICs
From: Volker Nicolai <Volker.Nicolai@philips.com>
Date: Thu, 03 Feb 2000 09:08:30 +0100
Links: << >>  << T >>  << A >>
Hi,

I asked this question at sci.electronics.design already and was sent
here:

I'm looking for the best solution of crossing clock domain boundaries in

digital designs solving the related timing problems.
In scan pathes lock-up latches are common (like Synopsys inserts them
during scan insertion).
Why negative (level triggered) latches instead of negative (edge
triggered) FFs? Is the setup/hold problem at the FALLING clock edge the
reason. which I do not have with latches (according to my simulations) ?

Couldn't I use them in functional pathes too?
Should I more concentrate on the adjustment of the clocks of the
different modules in my design or more on the datapathes. It seems easy
if the datapath is unidirectional but if it goes in both directions?

More detailed: At the moment I have clocks which have a common frequency
base (like 32 Mhz and 64 Mhz). The phase relation is
at least not yet predictable as the clocks are driven by seperate
clocktrees (for each frequency) which we not yet have
inserted. I look for a solution to avoid problems with clock adjustment
after layout (clock tree insertion) and the timing on
pathes that originate in one domain and end at the other.

Any comments, help or hints for information sources are very welcome.
Volker


Article: 20268
Subject: please help me
From: Jamil Khaib <Khatib@ieee.org>
Date: Thu, 03 Feb 2000 10:23:04 +0200
Links: << >>  << T >>  << A >>
Please help me,
I have designed a FIFO core for FPGA using schematic and VHDL. I got
good results using the schematics but the VHDL before synthesis I made
many archetectures and simulated all of them they gave me fine results
but after synthesizing them I got very bad results.

After synthesis, I got problem with the generation of Flages which
control the read and write operation. through simulationthe flages do
not change when an event is trigered  they can only be reseted the
simulator shows 'U' state all time except after reset.
why do I have this problem is there any thing with my VHDL code?
Note: I tried to synthesize the code on many synthesizers and targeted
to many PLD devices but all gave me the same results

Can you please help me

My main FIFO core page
http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo.html

The VHDL code which contains the 3 archs I synthesized FIFO_v4, FIFO_v5,
FIFO_v6
http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo_vhdl.html

These are the schematic results of the synthesized code generated by
siniplify
 http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo_v4.pdf
http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo_v5.pdf
http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo_v6.pdf

This is the wave form of the synthesized code
http://www.geocities.com/SiliconValley/Pines/6639/ip/wave.jpg

The FIFO project uses the idea of OpenIPCore desgin methodology

You can get the VHDL code and the test vectors from OpenCores CVS

Thanks in advance
Jamil Khatib
OpenIP Organization http://www.openip.org
OpenIPCore Project http://www.openip.org/oc
OpenCores  Project  http://www.opencores.org

Article: 20269
Subject: wrong ID from XC9536
From: "Klee" <wike@tu-bs.de>
Date: Thu, 3 Feb 2000 09:41:25 +0100
Links: << >>  << T >>  << A >>
hello,

I build the evaluationboard for Xilinx XC9536
(http://www.xilinx.com/xapp/xapp078.pdf)
and the JTAG-cable (http://www.xilinx.com/support/programr/jtag_cable.pdf)
but it won't work.
every time I try to download a jed-file, the target answered the
component-ID :
11111111000000000000000000000011
and this seems not to be a Xilinx-ID (second bit must be zero).

I checked the hardware several time, but I didn't found an error.
-> is there a simple solution which is not commented in application notes?

Wilken Klee


LOG-file:
JTAG Programmer Started 2000/02/03 09:33:50
Loading Boundary-Scan Description Language (BSDL) file
'c:/progs/xilinx/cpld/xc9500/data/xc9536.bsd'.....completed successfully.
Checking boundary-scan chain integrity...done.
Verifying device positions in boundary-scan chain...
Instance 'eval(Device1)' at position '1'...ERROR:JTag - The IDCODE returned
(11111111000000000000000000000011) indicates that the instance
'eval(Device1)' in the boundary-scan chain is not a Xilinx part.
failed.
Verification completed.
ERROR:JTag - Boundary scan chain has been improperly specified.  Please
check your configuration and re-enter the boundary-scan chain information.
Boundary-scan chain validated unsuccessfully.
ERROR:JTag - : The boundary-scan chain has not been declared correctly.
 Verify the syntax and correctness of the device BSDL files, correct the
files,
 reset the cable and retry this command.



Article: 20270
Subject: Re: Visualizing EDIF netlist for Xilinx
From: "Rémi SEGLIE" <rseglie@celogic.com>
Date: Thu, 3 Feb 2000 11:15:40 +0100
Links: << >>  << T >>  << A >>

"Allan Herriman" <allan.herriman.hates.spam@fujitsu.com.au> a écrit dans le
message news: 3899167f.8127266@newshost.fujitsu.com.au...
> On Wed, 02 Feb 2000 22:18:17 GMT, "Mikhail Matusov"
> <matusov@ANNTIsquarepegSPPAMM.ca> wrote:
>
> >Hi,
> >
> >I have recently started working with Xilinx Foundation tools and I am
still
> >on the learning curve with VHDL. My previous experience is AHDL for
Altera.
> >
> >I am having troubles understanding what synthesis does with the code I
write
> >so I would like to be able to see it somehow in the schematic or similar
> >format. I know that Sinplify has this option but I am not going to have
it
> >in the hear future. Is there any way to do this apart from manual
> >reconstructing schematics from the EDIF netlist?
> >
> >I will appreciate any input on this matter. Thanks.
> >
> >Mikhail Matusov
>
> Any reason why you can't get an evaluation copy of synplify?
> The guy sitting at the desk next to mine just got one, and seems quite
> impressed by the schematic viewer.
>
> Regards,
> Allan.

You have a schematic viewer  in FPGA Express too (so in Fondation Express).


Article: 20271
Subject: Spartan 2 & Foundation
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Thu, 03 Feb 2000 11:21:04 +0100
Links: << >>  << T >>  << A >>
Hi
I am trying to implement a design in a Spartan 2 device. I (think I)
updated Foundation to enable these devices but I still don't manage to
do it.
When I want to synthesize (with FPGA Express) my design, I can not
choose the Spartan2 family (the family is not in the list). A Xilinx FAE
told me to choose Virtex family for synthesis and then Spartan2 for
mapping and P&R but I don't know where to do this.
If anyone can help...
Thanks in advance

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 20272
Subject: Renoir problem: several engineers sharing a common setup?
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 03 Feb 2000 10:49:01 GMT
Links: << >>  << T >>  << A >>
I'm having a problem figuring out how to get a group of people to
share a common set of setups for Renoir.

(i) Engineer A works locally, and creates or modifies library A on
machine A.

(ii) Engineer B creates/modifies library B on machine B.

(iii) A and B use a revision control system that archives onto server
S.

(iv) Engineer C now needs access to libraries A and B, and so checks
them out of the archive.

Problem: engineer C cannot use the libraries. The reason is that
Renoir has 2 local initialisation and preferences files, which are
different for libraries A and B. These files contain information on
library usage and changes. To fix this problem, all the engineers have
to use a common copy of one initialisation and one profile file,
referencing all the libraries, with the masters on the server.

However, this doesn't work well. If engineer C checks outs the
initialisation files from the server, then they're locked, and no-one
else can modify them. Engineers A and B can actually use Renoir at the
same time but, when Renoir exits, it realises that the files are
locked by C, and so it silently creates a new local copy of the files,
which screws up the archiving, as well as potentially losing any
changes.

In short, there doesn't seem to be a way for multiple engineers to use
a common set of libraries, which is pretty annoying if you're bought
several licences. One fix might be to allow each engineer to have
access to only one library at a time, with each library having its own
initialisation files, but then you have to mess around with
environment variables to point to the required initialisation files.
Has anyone come across this?

Thanks

Evan


Article: 20273
Subject: Re: Renoir problem: several engineers sharing a common setup?
From: dej@coup.inode.org (David Jones)
Date: Thu, 03 Feb 2000 12:31:50 GMT
Links: << >>  << T >>  << A >>
In article <38995b2c.93043005@news.dial.pipex.com>,
 <eml@riverside-machines.com.NOSPAM> wrote:
>However, this doesn't work well. If engineer C checks outs the
>initialisation files from the server, then they're locked, and no-one
>else can modify them. Engineers A and B can actually use Renoir at the
>same time but, when Renoir exits, it realises that the files are
>locked by C, and so it silently creates a new local copy of the files,
>which screws up the archiving, as well as potentially losing any
>changes.

Is this locking done by Renoir, or the version control tool?  Is Renoir
sensitive to the actions of the version control in any way?

Most version control tools are highly unsuited to I.C. design; you need to
find one that will let you share objects in a read-only manner.


Article: 20274
Subject: Re: Visualizing EDIF netlist for Xilinx
From: Ernest Jamro <jamro@uci.agh.edu.pl>
Date: Thu, 03 Feb 2000 15:17:45 +0100
Links: << >>  << T >>  << A >>
>
> You have a schematic viewer  in FPGA Express too (so in Fondation Express).

Could you please let me know how to enter the schematic viewer program
in Foundation 2.1. Because I cannot find nothing like that.

--
----------- Ernest Jamro ------------
e-mail: jamro@uci.agh.edu.pl
Address: AGH Technical University, Institute of Electronics
Mickiewicza 30; 30-059 Kraków; Poland; tel. 48-12-617-2792




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search