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Messages from 20275

Article: 20275
Subject: Re: Can hobbyist buy altera in uk?
From: "Stewart, Nial [HAL02:HH00:EXCH]" <stewartn@europem01.nt.com>
Date: Thu, 03 Feb 2000 15:42:54 +0000
Links: << >>  << T >>  << A >>
Tim Tyler wrote:
> =

> funky jim <jmc8197@hotmail.com> wrote:
> =

> : Does any place in the UK sell Altera devices to the hobbyist.
> =

> To quote from http://ftp.altera.com/html/office.6.html
> =

> UNITED KINGDOM:
> =

> Ambar-Cascom, Ltd.
> The Gatehouse
> Gatehouse Way
> Aylesbury, Buckinghamshire
> HP19 3DL
> United Kingdom
> =

> Flexible Logic (Arrow)
> St.Martins Business Centre
> Cambridge Road
> Bedford
> MK42 0LF
> United Kingdom
> =

> Thame Components, Ltd.
> Thame Park Road
> Thame
> Oxfordshire
> OX9 3UQ
> United Kingdom
> URL: http://www.tcl.memec.com/
> =

> [I snipped out phone numbers and email addresses so I'm less responsibl=
e
> for any spam these folks get.  See the original page for these.]
> =

> The URL at the end has lots of Altera bits and pieces - but they don't
> seem to be stuck together very much.
> =

> http://www.computer-solutions.co.uk/ also have Altera parts, I believe.=

> =

> This information is probably of low quality - but it's the best I can
> manage :-|

One thing I would add to this is check prices before you decide what
you're
going to use. I was using EPM7096's which aren't isp compatible and
which
cost =A325 until I found I could buy the bigger EPM7128S which is isp =

compatible for =A311. You can also get them through Farnell for about the=

same price.

Nial.
Article: 20276
Subject: VHDL and Xilinx Books for beginners
From: "Holger Kleinert" <Kleinert@ibpmt.com>
Date: Thu, 3 Feb 2000 17:15:00 +0100
Links: << >>  << T >>  << A >>
Hi All!

What book do you recommend for beginners in VHDL Programming, which are
using XILINX Foundation 2.1i.
I am interested in  books written in englisch or german language.

Thank you for suggestions.

--
Holger Kleinert
Development / Support

IBP Instruments GmbH
Sutelstrasse 7a
D-30659 Hannover, Germany

http://www.ibpmt.com
Fon : +49-511-651647
Fax : +49-511-652283






Article: 20277
Subject: Re: Visualizing EDIF netlist for Xilinx
From: "Rémi SEGLIE" <rseglie@celogic.com>
Date: Thu, 3 Feb 2000 17:30:58 +0100
Links: << >>  << T >>  << A >>
Hi,

I haven't "Foundation 2.1."  but ViewLogic CAO (Schematic, FPGA Express and
so on) + Alliance 2.1 (Xilinx)

With ViewLogic, it's an option to have schematic in FPGA Express. Ask your
tech. support to know if it's not the same.
(If you have schematic viewer, you normally right click in the "chip window"
and "View Schematic", if you bought the option, it's work !)

"Ernest Jamro" <jamro@uci.agh.edu.pl> a écrit dans le message news:
38998E08.A189F4E5@uci.agh.edu.pl...
> >
> > You have a schematic viewer  in FPGA Express too (so in Fondation
Express).
>
> Could you please let me know how to enter the schematic viewer program
> in Foundation 2.1. Because I cannot find nothing like that.
>
> --
> ----------- Ernest Jamro ------------
> e-mail: jamro@uci.agh.edu.pl
> Address: AGH Technical University, Institute of Electronics
> Mickiewicza 30; 30-059 Kraków; Poland; tel. 48-12-617-2792
>
>


Article: 20278
Subject: Re: VHDL and Xilinx Books for beginners
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 03 Feb 2000 11:38:29 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0C23D22D8DD6CFF218436222
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Holger Kleinert wrote:

> Hi All!
>
> What book do you recommend for beginners in VHDL Programming, which are
> using XILINX Foundation 2.1i.
> I am interested in  books written in englisch or german language.
>
> Thank you for suggestions.
>

I'll give you my suggestions:

"The Practical Xilinx Designer Lab Book" has many of the examples
done with VHDL.  That's a decent place to start if you are working
specifically with the Xilinx Foundation tools.

"VHDL for Programmable Logic" by Kevin Skahill is a good book.
It is oriented toward Cypress devices and their Warp tools.

Both of the books listed above discuss a subset of the VHDL language
that's sufficient to get started.  "The Designer's Guide to VHDL" by
Ashenden is my bible for VHDL.  It works very well as a reference.

You can also check the "Related Books" link at http://www.optimagic.com for a list of VHDL books.  Also check the "HDL Tutorials " link for online stuff you can get for free.


--------------0C23D22D8DD6CFF218436222
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
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begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------0C23D22D8DD6CFF218436222--

Article: 20279
Subject: Re: Xilinx Virtex Decoupling Cap Guidelines
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Thu, 03 Feb 2000 10:51:18 -0800
Links: << >>  << T >>  << A >>
As they say, their recommendation was intended to cover a broad
variety of applications. In your particular application, you
might be able to get away with less, especially if you are not using many
output drivers. You might want to look
at the AVX SMT tantalum catalog (download pdf from
http://www.avxcorp.com/products/capacitors/smtc.htm) for
quantative info on ESR v.s. size for this line of caps. It looked
like (as I recall) about 100 milliohms for 470 uF, v.s. 3-400 milliohms
for the 47 uF. (at 100 KHz). For board layout, I would try to follow
the recommendation, and then, if the application was cost sensitive,
experiment with removing the big cap while measuring worst case power
plane noise at the part.

As for startup in your low-power app, you should (if you haven't already)
read the "Power-On Power Supply Requirements" section of the data sheet
(bottom of p. 24 in the DS003 v1.7 sheet). Essentially, it says that
Virtex parts need lots of current (0.5 to 2A) during power-up, which is
good to know early in the design process :) And don't forget the 50 ms max.
supply ramp-up time.

regards, tom 


John Janusson wrote:
> 
> Hello:
> 
> I have read XAPP158 (Powering Virtex FPGAs
> http://www.xilinx.com/xapp/xapp158.pdf) and found the following
> recommendations:
> 
> VCCINT    ->    Guideline
> -------------------
> 0.1 uF    ->    One per VCC
> 47 uF    ->    Four per device (XCV50 - XCV300)
> 470 uF    ->    One per device
> 
> 470uF!!!  In my experience, this seems excessive, even after reading the
> disclaimer in Answers record #777
> (http://support.xilinx.com/techdocs/777.htm)...  I was planning on following
> the guidelines sans 470uF cap.  It's a low power design in a XCV100 running
> at mostly 4 to 32 MHz...
> 
> Can others comment on power related issues in Virtex parts, particularly
> related to decoupling and startup???
> 
> Thanks...
> 
> John

-- 
Tom Burgess
-- 
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Email:        tom.burgess@hia.nrc.ca
Office:       (250) 490-4360 
Switch Board: (250) 493-2277
Fax:          (250) 493-7767
Article: 20280
Subject: capacitor !
From: "Klee" <wike@tu-bs.de>
Date: Thu, 3 Feb 2000 21:13:37 +0100
Links: << >>  << T >>  << A >>
only 10pF from TCK to GND and I can read the correct ID (and I can read
signatur&user-code)

but I still can't program this CPLD. It seems that my board is not routed
fine.


LOG-file:
'eval(Device1)': Programming device....ERROR:JTag - The program operation
failed for instance 'eval(Device1)' when attempting to address location
'0x12492'.
 The part appears to be in read or write protect mode.
 You will have erase the part the disable this mode.
--> If the part is not in this mode then check that the target system power
supply is stable, adequate and at the correct level.
 In addition make certain that each device has adequate decoupling. <--



Article: 20281
Subject: Re: Visualizing EDIF netlist for Xilinx
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Thu, 03 Feb 2000 20:47:06 GMT
Links: << >>  << T >>  << A >>
Thanks to everybody for the input. I tried VISTA viewer in the FPGA Express
and it works not bad at all.

MM


Article: 20282
Subject: Re: Xilinx Virtex Decoupling Cap Guidelines
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 03 Feb 2000 15:56:01 -0500
Links: << >>  << T >>  << A >>
John Janusson wrote:
> 
> Hello:
> 
> I have read XAPP158 (Powering Virtex FPGAs
> http://www.xilinx.com/xapp/xapp158.pdf) and found the following
> recommendations:
> 
> VCCINT    ->    Guideline
> -------------------
> 0.1 uF    ->    One per VCC
> 47 uF    ->    Four per device (XCV50 - XCV300)
> 470 uF    ->    One per device
> 
> 470uF!!!  In my experience, this seems excessive, even after reading the
> disclaimer in Answers record #777
> (http://support.xilinx.com/techdocs/777.htm)...  I was planning on following
> the guidelines sans 470uF cap.  It's a low power design in a XCV100 running
> at mostly 4 to 32 MHz...
> 
> Can others comment on power related issues in Virtex parts, particularly
> related to decoupling and startup???
> 
> Thanks...
> 
> John

This is the third time I have attempted to reply to this posting. The
other two got lost in the ether. Maybe I should just keep my mouth shut?

My opinion is that Xilinx is practicing some serious overkill without
good justification. Their note about not knowing what the different
designs are doing is real, but there are rules of physics that
electronics follow. 

The series inductance of most capacitors other than ceramic chip caps is
significant at any frequency above about 1 MHz. Some specify the ESR at
100 KHz. The series inductance of these caps is large enough that the
size of the capacitor or the location or quantity of parts is not
significant for typical switching noise which is in the range well above
100 MHz. So for switching noise, only ceramic chip caps located close to
your power and ground pins will do a good job. Further these caps are
inductive at the significant frequencies. The graph in the Xilinx app
note show that the impedance above 100 MHz is not significantly
different between same size parts with different capacitance. So it
really doesn't make much difference if you use 0.1 uF or 0.01 uF caps.
But certainly using 0.1 uF caps make you feel better, I know it does me
:) But the cap size does make a real difference. Smaller is generally
better, but wider makes more of a difference according to the
manufacturer's data. 

So I would not recommend that you use multiple large capacitors. Rather
use one large (and 470 uF is really large) value tantalum cap near the
power connector for each supply voltage. Then use a 0.01 to 0.1 uF cap
as close as possible to each power and ground pin pair. I ended up with
some 90 pieces of 0.1 uF caps on my board giving me a total of about 4 -
5 uF per supply voltage in high freq decoupling. And it was a very small
board, PC/104!

The large capacitors are only good for lower freq signals. My 5 to 3
volt power converter only has 100 uF on the output for the 300 KHz
switching freq. With that there is only about 20 - 30 mV of noise from a
1.5 Amp supply. So I don't think you need a lot more for chip
decoupling. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20283
Subject: Re: Renoir problem: several engineers sharing a common setup?
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 03 Feb 2000 21:17:54 GMT
Links: << >>  << T >>  << A >>
On Thu, 03 Feb 2000 12:31:50 GMT, dej@coup.inode.org (David Jones)
wrote:

>In article <38995b2c.93043005@news.dial.pipex.com>,
> <eml@riverside-machines.com.NOSPAM> wrote:
>>However, this doesn't work well. If engineer C checks outs the
>>initialisation files from the server, then they're locked, and no-one
>>else can modify them. Engineers A and B can actually use Renoir at the
>>same time but, when Renoir exits, it realises that the files are
>>locked by C, and so it silently creates a new local copy of the files,
>>which screws up the archiving, as well as potentially losing any
>>changes.
>
>Is this locking done by Renoir, or the version control tool?  Is Renoir
>sensitive to the actions of the version control in any way?

The VC tool (MKS's Source Integrity) does the locking, and Renoir
doesn't know anything about it, other than noticing the read-only
attribute when it eventually tries to write the preferences file. 

In principle, Renoir could handle the version control itself. It does
this by writing scripts for RCS, but I don't think that this would
help. An individual user would still have to lock the global
preferences file in order to get write access to it, and this would
lock out the other users.

In practice, Renoir is only used on a small part of the project
anyway, and so it couldn't be used for VC since it doesn't know about
the rest of the project.

>Most version control tools are highly unsuited to I.C. design; you need to
>find one that will let you share objects in a read-only manner.

I'm not sure that this is the problem - everyone can read the
preferences file; it's just that Renoir's not intelligent enough to
realise that multiple users might want to write to the preferences
file. 

I think the answer might be that there's no way to have a global
setup. Each designer has a local renoir.ini and .renoirprefs for each
library, and these are archived together with that particular library.
A user on another machine who needs the library checks it out together
with its own ini and prefs file, and then runs Renoir with the
-inifile and -prefsfile options pointing to the local files. This
should give access to the local library and preserve the original
designer's downstream tool settings, and so on. I'll give this a go to
see if it works.

Evan

Article: 20284
Subject: Re: Renoir problem: several engineers sharing a common setup?
From: Phil Cole <pcole@net.com>
Date: Thu, 03 Feb 2000 14:39:37 -0800
Links: << >>  << T >>  << A >>
We're doing what you want to do.

In one project there are 23 libraries and up
to 15 developers (including test bench and test code
developers).

We are using NT and Solaris platforms and sharing the
file systems containing the controlled source.

The way we did it was to have a template renoirPrefs
which the designers copy to their local ~/.renoirPrefs
(or the equivalent place for NT). renoirPrefs mostly
controls generate styles, editor selection and other stuff
users have their own dogmas about. Mistakes in renoirPrefs
generally just prevent developers from proceeding with
their task until they figure it out. The project is not
messed with. We've never had to change renoirPrefs during
the project.

The renoir.ini (which contains the lib mappings mostly)
is selected by setting the $RENOIRLIBS variable in each users
environment to the same value. Changing libraries around or adding them requires
the renoir.ini be checked out and changed by hand. This does
not happen often, and can usually be managed in a backward 
compatible way.

We're using clearcase for source control, and while Renoir
can interwork with it, renoir 99.2 makes messes during check in
so we do it manually.

We use release labels so that individuals can select tested working
versions of everything but the stuff they're directly working on.

There's a pre-release mechanism used to regress newly checked in
source against the rest of the system before it's released for
generaly use. SW folks mastered all this sort of stuff a long time
ago and we just do what they do.

eml@riverside-machines.com.NOSPAM wrote:
> 
> I'm having a problem figuring out how to get a group of people to
> share a common set of setups for Renoir.
> 
> (i) Engineer A works locally, and creates or modifies library A on
> machine A.
> 
> (ii) Engineer B creates/modifies library B on machine B.
> 
> (iii) A and B use a revision control system that archives onto server
> S.
> 
> (iv) Engineer C now needs access to libraries A and B, and so checks
> them out of the archive.
> 
> Problem: engineer C cannot use the libraries. The reason is that
> Renoir has 2 local initialisation and preferences files, which are
> different for libraries A and B. These files contain information on
> library usage and changes. To fix this problem, all the engineers have
> to use a common copy of one initialisation and one profile file,
> referencing all the libraries, with the masters on the server.

The common renoir.ini refers to all the libraries, so all developers
can see all the libraries all the time, even if they are only working
on stuff in one of them. If you want to test against a complete system,
you'd need all the libraries available anyway.

> 
> However, this doesn't work well. If engineer C checks outs the
> initialisation files from the server, then they're locked, and no-one
> else can modify them. Engineers A and B can actually use Renoir at the
> same time but, when Renoir exits, it realises that the files are
> locked by C, and so it silently creates a new local copy of the files,
> which screws up the archiving, as well as potentially losing any
> changes.

Why not just check out the files you need? You generally don't need the
all the source files in a library.

To make this work, people will be generating their own local copies of
the generated files and vhdl libs. In Clearcase each user can have his
own set of private files which have the same path name as another
user's, but completely different content. Only files explicitly made
into source controlled elements are common to everyone. If your
source control can't do this, then the paths for the generated and
vhdl libraries in renoir.ini will have to have a user-unique variable.

e.g.

[renoir_library]
lib_1   /source_control_file_system/$PROJECT/lib_1/renoir
lib_2   /source_control_file_system/$PROJECT/lib_2/renoir

[generated_library]
lib_1   $USER/objects/lib_1/vhdl.gen
lib_2   $USER/objects/lib_2/vhdl.gen

[library]
lib_1   $USER/objects/lib_1/vhdl.lib
lib_2   $USER/objects/lib_2/vhdl.lib

Clearcase can use derived objects to
permit sharing of object files, but we never bothered in HW because the
build times are not that long, and each user only needs about 1 Gbyte of
private storage for objects.


PHil
Article: 20285
Subject: Re: Count 1's algorithm...
From: gillies@cs.ubc.ca (Donald Gillies)
Date: 3 Feb 2000 14:42:17 -0800
Links: << >>  << T >>  << A >>
I believe (if i remember correctly), that counting 1's in an "intense"
problem in planar vlsi because the circuit complexity is at least as
great as parity (remember the parity function is just the lowest bit
of a "bitcount" function), and parity circuit complexity is similar to
multiplication.  And we have non-trivial lower bounds on circuit
complexity for mulutiplication (courtesy Andy Yao).

So, just warning you that this one of the more difficult problems in
VLSI and don't expect to get a screaming fast solution.

A common software algorithm is to build a tree of recursive adders to
add every pair of bits (in parallel), then add every pair of sums (in
paralle), add every pair of sums ... until you get just one sum.
Depth is O( log(bits) ), and the adders can be very stupid.  No adder
needs to be more than log(bits) in size.

A more complex software algorithm is to use subtractors and add groups
of 3 bits in the first stage.  If x = 4a + 2b + c, then x - x>>1 -
x>>2 = a+b+c.

Then, you have a sum (0..3) and this is in the right range to minimize
gates in all the downstream stages.

- Don
Article: 20286
Subject: Re: Xilinx Virtex Decoupling Cap Guidelines
From: bobperl@best_no_spam_thanks.com (Bob Perlman)
Date: Thu, 03 Feb 2000 23:35:49 GMT
Links: << >>  << T >>  << A >>
Hi - 

Those of you in the Bay Area who are interested in bypassing and other
power distribution issues may be want to attend next week's IEEE EMC
Society meeting.  The notice that appears below was posted to the
signal integrity reflector this AM.

Take care,
Bob Perlman

--------------------------------------------------------------------------------------

The Santa Clara Valley Chapter of the EMC Society is
presenting on the 8th of February, 2000

Simultaneous Switch Noise and Power Plane Bounce, by
Larry Smith, Sun Microsystems.

Free admission, all welcome.

5:30-7:30 pm. social, food and refreshements (there is
a charge for food and refreshements) 

7:30-8:30 pm. Presentation:

Simultaneous Switch Noise (SSN) has traditionally been
thought of as an inductance problem.  Modern
electronic packages with solder bumps, solder balls
and power planes have very low inductance.  The SSN
problem is shifting from an inductance problem to a
power plane bounce problem.  Return current from
signal transmission lines can be used to explain and
account for power plane bounce.  Noisy power planes
are
known to be the root cause of many SI and EMI
problems.  The key to managing power plane bounce is
in managing return currents and power plane
decoupling.

Larry D Smith received the BSEE degree from Rose
Hulman Institute of Technology in 1975 and the MS
dregree in Material Science from the University of
Vermont in 1983.  After joining IBM in 1978, he worked
in the areas of reliability, characterization, failure
analysis, power supply and analog curcuit design,
packaging and signal integrity at Sun Microsystems
since 1996.  His current area of concentration is
design of power distribution systems and reduction of
simultaneous switch noise.

SCV IEEE EMC Society Dinner & Meeting Locations
The dinner and meeting  will be held at the Silicon
Graphics’ Café Iris, Building 5, on 2025 Stierlin
Court in Mountain View, CA. 

For additional information and directions visit our
website:

www.scvemc.org





-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 20287
Subject: Re: Can hobbyist buy altera in uk?
From: "funky jim" <jmc8197@hotmail.com>
Date: Fri, 4 Feb 2000 00:59:33 -0000
Links: << >>  << T >>  << A >>
Just found out that RS have a good range also.

Stewart, Nial [HAL02:HH00:EXCH] <stewartn@europem01.nt.com> wrote in message
news:3899A1FE.E0939579@europem01.nt.com...
Tim Tyler wrote:
>
> funky jim <jmc8197@hotmail.com> wrote:
>
> : Does any place in the UK sell Altera devices to the hobbyist.
>
> To quote from http://ftp.altera.com/html/office.6.html
>
> UNITED KINGDOM:
>
> Ambar-Cascom, Ltd.
> The Gatehouse
> Gatehouse Way
> Aylesbury, Buckinghamshire
> HP19 3DL
> United Kingdom
>
> Flexible Logic (Arrow)
> St.Martins Business Centre
> Cambridge Road
> Bedford
> MK42 0LF
> United Kingdom
>
> Thame Components, Ltd.
> Thame Park Road
> Thame
> Oxfordshire
> OX9 3UQ
> United Kingdom
> URL: http://www.tcl.memec.com/
>
> [I snipped out phone numbers and email addresses so I'm less responsible
> for any spam these folks get.  See the original page for these.]
>
> The URL at the end has lots of Altera bits and pieces - but they don't
> seem to be stuck together very much.
>
> http://www.computer-solutions.co.uk/ also have Altera parts, I believe.
>
> This information is probably of low quality - but it's the best I can
> manage :-|

One thing I would add to this is check prices before you decide what
you're
going to use. I was using EPM7096's which aren't isp compatible and
which
cost £25 until I found I could buy the bigger EPM7128S which is isp
compatible for £11. You can also get them through Farnell for about the
same price.

Nial.


Article: 20288
Subject: Re: Count 1's algorithm...
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Feb 2000 01:09:41 GMT
Links: << >>  << T >>  << A >>
In VLSI, counting 1's isn't that bad.  It is just a tally adder, which in
merged tree form is basically a wallace tree with one bit wide input
'columns'.  Delay is a log(n) problem.   The classic optimal merged tree
has 2x2 blocks (2 input gates, each fanning out to 2 destinations).  The
FPGA structure usually supports more than that, so you can improve it by
taking advantage of the architecture.  Also, the fast carry chains in the
FPGA skew the optimal solution.

Donald Gillies wrote:

> I believe (if i remember correctly), that counting 1's in an "intense"
> problem in planar vlsi because the circuit complexity is at least as
> great as parity (remember the parity function is just the lowest bit
> of a "bitcount" function), and parity circuit complexity is similar to
> multiplication.  And we have non-trivial lower bounds on circuit
> complexity for mulutiplication (courtesy Andy Yao).
>
> So, just warning you that this one of the more difficult problems in
> VLSI and don't expect to get a screaming fast solution.
>
> A common software algorithm is to build a tree of recursive adders to
> add every pair of bits (in parallel), then add every pair of sums (in
> paralle), add every pair of sums ... until you get just one sum.
> Depth is O( log(bits) ), and the adders can be very stupid.  No adder
> needs to be more than log(bits) in size.
>
> A more complex software algorithm is to use subtractors and add groups
> of 3 bits in the first stage.  If x = 4a + 2b + c, then x - x>>1 -
> x>>2 = a+b+c.
>
> Then, you have a sum (0..3) and this is in the right range to minimize
> gates in all the downstream stages.
>
> - Don

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20289
Subject: Re: Spartan 2 & Foundation
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Feb 2000 02:12:03 GMT
Links: << >>  << T >>  << A >>
If you are not getting spartanII in the device list in the design manager,
you either didn't install it or you didn't install it right.  I think
installing the spartan II requires a new CD code which you get from the
Xilinx website.  If you are still using your original CD key code, the other
stuff still works, but you won't see the SpartanII parts.  Search on the
Xilinx website for SpartanII and look for the installation instructions.
IIRC, the procedure is spelled out in excruciating detail.  You need SP4 for
the timings, and you need to go through the install procedure after patching
with SP4 to enable the spartanII (for that you also need the new key code).

Nicolas Matringe wrote:

> Hi
> I am trying to implement a design in a Spartan 2 device. I (think I)
> updated Foundation to enable these devices but I still don't manage to
> do it.
> When I want to synthesize (with FPGA Express) my design, I can not
> choose the Spartan2 family (the family is not in the list). A Xilinx FAE
> told me to choose Virtex family for synthesis and then Spartan2 for
> mapping and P&R but I don't know where to do this.
> If anyone can help...
> Thanks in advance
>
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20290
Subject: Re: Anyone changed an NT disk serial number?
From: "Austin Franklin" <austin@dar88kroom.com>
Date: 4 Feb 2000 02:46:39 GMT
Links: << >>  << T >>  << A >>
> The actual act of changing a serial number can't be illegal
> unless Microsoft forbids it in its licence agreement, 

Even if it is in a license agreement, it does not mean it is illegal.  Most
license agreements claim you can't disassemble the code, yet the courts
have upheld the position that is perfectly legal for you to do.  You own
the disk, you have the right to use the software.

If you are only using one copy of it at a time, and have not provided it to
anyone else, from what I understand the current laws to be, you are not
violating any laws.


Article: 20291
Subject: Re: Xilinx Virtex Decoupling Cap Guidelines
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Fri, 04 Feb 2000 04:05:25 GMT
Links: << >>  << T >>  << A >>
On Thu, 03 Feb 2000 15:56:01 -0500, Rickman <spamgoeshere4@yahoo.com>
wrote:

[snip]
>So I would not recommend that you use multiple large capacitors. Rather
>use one large (and 470 uF is really large) value tantalum cap near the
>power connector for each supply voltage. Then use a 0.01 to 0.1 uF cap
>as close as possible to each power and ground pin pair. I ended up with
>some 90 pieces of 0.1 uF caps on my board giving me a total of about 4 -
>5 uF per supply voltage in high freq decoupling. And it was a very small
>board, PC/104!
[snip]

Hey Rick, like what you say, except for the bit about the tantalum cap
needing to be near the power connector.  It really doesn't matter
where it goes on the board.  As you say, it's only effective at lower
frequencies.  Also, its ESR will be much higher than the plane
impedance.

Regards,
Allan.
Article: 20292
Subject: Re: Xilinx Virtex Decoupling Cap Guidelines
From: Andreas Heiner <Andreas.Heiner@de.bosch.com>
Date: Fri, 4 Feb 2000 09:34:56 +0100
Links: << >>  << T >>  << A >>


> My opinion is that Xilinx is practicing some serious overkill without
> good justification. Their note about not knowing what the different
> designs are doing is real, but there are rules of physics that
> electronics follow.
>

I would agree with your opinon. The app note is really stupid. If you would
place all the caps araound the device, you are not able to connect the
device, or you loose the bottom of the PCB. We're using Xilinx FPGA for a
long time (from XC4xxx up to XCV800) and we don't have had any problems with
it. The design of the PCB is more important than the cap's araound it. For
EMI-Problems not every time a lot of cap's are really good. A very good
solution is the use a wide band decoupling. The way for this is:
1. Use multilayer PCB nboards with seperate power planes
2. Create "island's" for the device
3. calculate with the characteristics of the PCB (Er, distance of layer's,
etc.) the correct cap's for a wideband filter.

The result is, that only one big cap (220 - 470 uF) can be used for the
power input of the board. Then, for the island of the FPGA only a group of
up to 6 small cap's (10pF...1uF) are neccessary.

The wide band decoupling is developed by Prof. Dirks, the calculation
program calls "SILENT". If you want more info, just contact him at
EMVProf@aol.com.


Andreas Heiner


Article: 20293
Subject: PMUX primitive in Sinplify
From: boniolopez@my-deja.com
Date: Fri, 04 Feb 2000 08:59:56 GMT
Links: << >>  << T >>  << A >>
Hi friends,
I am evaluating  Synplify now.
They have very good RTL viewer.
But one of the components, I have found in there
I can't find in XILINX primitives.
I speak about PMUX. I think this is a priority
MUX.  If the E input =1 the output is
equal  D input (Am I right?). But what will be if
two E inputs are one?
Can anybody send me the LUT or describe the
function of this primitive.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20294
Subject: Re: Spartan 2 & Foundation
From: "Jean-Paul GOGLIO" <goglio@getris.alpes-net.fr>
Date: Fri, 4 Feb 2000 10:09:58 +0100
Links: << >>  << T >>  << A >>

Ray Andraka wrote <389A359A.2CBBEAA9@ids.net>...
>If you are not getting spartanII in the device list in the design manager,
>you either didn't install it or you didn't install it right.  I think
>installing the spartan II requires a new CD code which you get from the
>Xilinx website.  If you are still using your original CD key code, the
other
>stuff still works, but you won't see the SpartanII parts.  Search on the
>Xilinx website for SpartanII and look for the installation instructions.
>IIRC, the procedure is spelled out in excruciating detail.  You need SP4
for
>the timings, and you need to go through the install procedure after
patching
>with SP4 to enable the spartanII (for that you also need the new key code).
>
>Nicolas Matringe wrote:
>
>> Hi
>> I am trying to implement a design in a Spartan 2 device. I (think I)
>> updated Foundation to enable these devices but I still don't manage to
>> do it.
>> When I want to synthesize (with FPGA Express) my design, I can not
>> choose the Spartan2 family (the family is not in the list). A Xilinx FAE
>> told me to choose Virtex family for synthesis and then Spartan2 for
>> mapping and P&R but I don't know where to do this.
>> If anyone can help...
>> Thanks in advance
>>
>> Nicolas MATRINGE           DotCom S.A.
>> Conception electronique    16 rue du Moulin des Bruyeres
>> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
>> Fax 00 33 1 46 67 51 01    FRANCE
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>

Hi everybody,

I have exactly the same problem with Foundation 2.1i sp4 when i try to
synthesize or to implement a design on a Spartan II.
2 months a go, i got a new CD Key code from the xilinx website to use Virtex
E chips.
I have no trouble with making a synthesis / implementation on Virtex E
Chips.
1 month a go, i tried to make a synthesis on Spartan II chips, this family
was not on the list.
I tried to get a new CD key code from the xilinx website to use Spartan II,
i got exactly the same code as the Virtex -E one.
I made a full unistallation / installation of Foundation, then of SP4 with
the new CD code, it still doesn't work. for Spartan II, and it still works
for Virtex E.
(I use Windows NT).

What am i doing wrong ?

J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com








Article: 20295
Subject: Re: Spartan 2 & Foundation
From: "Jean-Paul GOGLIO" <goglio@getris.alpes-net.fr>
Date: Fri, 4 Feb 2000 10:09:58 +0100
Links: << >>  << T >>  << A >>

Ray Andraka wrote <389A359A.2CBBEAA9@ids.net>...
>If you are not getting spartanII in the device list in the design manager,
>you either didn't install it or you didn't install it right.  I think
>installing the spartan II requires a new CD code which you get from the
>Xilinx website.  If you are still using your original CD key code, the
other
>stuff still works, but you won't see the SpartanII parts.  Search on the
>Xilinx website for SpartanII and look for the installation instructions.
>IIRC, the procedure is spelled out in excruciating detail.  You need SP4
for
>the timings, and you need to go through the install procedure after
patching
>with SP4 to enable the spartanII (for that you also need the new key code).
>
>Nicolas Matringe wrote:
>
>> Hi
>> I am trying to implement a design in a Spartan 2 device. I (think I)
>> updated Foundation to enable these devices but I still don't manage to
>> do it.
>> When I want to synthesize (with FPGA Express) my design, I can not
>> choose the Spartan2 family (the family is not in the list). A Xilinx FAE
>> told me to choose Virtex family for synthesis and then Spartan2 for
>> mapping and P&R but I don't know where to do this.
>> If anyone can help...
>> Thanks in advance
>>
>> Nicolas MATRINGE           DotCom S.A.
>> Conception electronique    16 rue du Moulin des Bruyeres
>> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
>> Fax 00 33 1 46 67 51 01    FRANCE
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>

Hi everybody,

I have exactly the same problem with Foundation 2.1i sp4 when i try to
synthesize or to implement a design on a Spartan II.
2 months a go, i got a new CD Key code from the xilinx website to use Virtex
E chips.
I have no trouble with making a synthesis / implementation on Virtex E
Chips.
1 month a go, i tried to make a synthesis on Spartan II chips, this family
was not on the list.
I tried to get a new CD key code from the xilinx website to use Spartan II,
i got exactly the same code as the Virtex -E one.
I made a full unistallation / installation of Foundation, then of SP4 with
the new CD code, it still doesn't work. for Spartan II, and it still works
for Virtex E.
(I use Windows NT).

What am i doing wrong ?

J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com








Article: 20296
Subject: Re: Spartan 2 & Foundation
From: "Jean-Paul GOGLIO" <goglio@getris.alpes-net.fr>
Date: Fri, 4 Feb 2000 10:09:58 +0100
Links: << >>  << T >>  << A >>

Ray Andraka wrote <389A359A.2CBBEAA9@ids.net>...
>If you are not getting spartanII in the device list in the design manager,
>you either didn't install it or you didn't install it right.  I think
>installing the spartan II requires a new CD code which you get from the
>Xilinx website.  If you are still using your original CD key code, the
other
>stuff still works, but you won't see the SpartanII parts.  Search on the
>Xilinx website for SpartanII and look for the installation instructions.
>IIRC, the procedure is spelled out in excruciating detail.  You need SP4
for
>the timings, and you need to go through the install procedure after
patching
>with SP4 to enable the spartanII (for that you also need the new key code).
>
>Nicolas Matringe wrote:
>
>> Hi
>> I am trying to implement a design in a Spartan 2 device. I (think I)
>> updated Foundation to enable these devices but I still don't manage to
>> do it.
>> When I want to synthesize (with FPGA Express) my design, I can not
>> choose the Spartan2 family (the family is not in the list). A Xilinx FAE
>> told me to choose Virtex family for synthesis and then Spartan2 for
>> mapping and P&R but I don't know where to do this.
>> If anyone can help...
>> Thanks in advance
>>
>> Nicolas MATRINGE           DotCom S.A.
>> Conception electronique    16 rue du Moulin des Bruyeres
>> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
>> Fax 00 33 1 46 67 51 01    FRANCE
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>

Hi everybody,

I have exactly the same problem with Foundation 2.1i sp4 when i try to
synthesize or to implement a design on a Spartan II.
2 months a go, i got a new CD Key code from the xilinx website to use Virtex
E chips.
I have no trouble with making a synthesis / implementation on Virtex E
Chips.
1 month a go, i tried to make a synthesis on Spartan II chips, this family
was not on the list.
I tried to get a new CD key code from the xilinx website to use Spartan II,
i got exactly the same code as the Virtex -E one.
I made a full unistallation / installation of Foundation, then of SP4 with
the new CD code, it still doesn't work. for Spartan II, and it still works
for Virtex E.
(I use Windows NT).

What am i doing wrong ?

J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
Fax : (33) 4 76 18 52 01
E-mail : goglio@getris.com








Article: 20297
Subject: RECHERCHE
From: "Joel BRUNEAU" <joel.bruneau@mors.fr>
Date: Fri, 4 Feb 2000 10:22:41 +0100
Links: << >>  << T >>  << A >>
5 A42MX16FPL84 ACTEL
5 A42MX24FPL84 ACTEL


Article: 20298
Subject: Re: Xilinx Tools
From: "David Hawke" <dhawke@skynow.net>
Date: Fri, 4 Feb 2000 09:51:00 -0000
Links: << >>  << T >>  << A >>
Keith,

Get in touch with either MicroCall(now insight) or Avnet in the UK.

F2.1i costs just $95 (DS-FND-BAS-PC) and the Vhdl/Vlog at $495
(DS-FND-BSX-PC)

Hope this helps,

Dave Hawke
Xilinx UK

Keith Wootten wrote in message ...
>Hi
>
>I've been using Foundation F1.4 for a while, using XC5215 and Spartan
>XCS40.  I want to change to the 3.3V XCS40XL part, but my software won't
>support this part.
>
>Apparently, there is no upgrade path for F1.4 and I'll have to *buy*
>some new software.  To cope with both the XC5215 and the XCS40XL parts,
>I'll need to spend over GBP1000 - yes, one kilopound.  I already spent
>over GBP2000 for the F1.4 stuff, and I'm not a volume user.
>
>Why do they do this?  Surely the small company user has *some* value?
>The support from the dealer was poor and the promised training sessions
>never materialised once the money was paid, so cost of support is no
>justification.
>
>Can anyone recommend a UK dealer who is not a shark?
>
>Cheers
>--
>Keith Wootten


Article: 20299
Subject: Re: Renoir problem: several engineers sharing a common setup?
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 04 Feb 2000 10:51:00 GMT
Links: << >>  << T >>  << A >>
Thanks Phil - this is very useful. I've got a couple of other
questions, if you don't mind:

>The way we did it was to have a template renoirPrefs
>which the designers copy to their local ~/.renoirPrefs
>(or the equivalent place for NT). renoirPrefs mostly
>controls generate styles, editor selection and other stuff
>users have their own dogmas about. Mistakes in renoirPrefs
>generally just prevent developers from proceeding with
>their task until they figure it out. The project is not
>messed with. We've never had to change renoirPrefs during
>the project.

Some users want Renoir to control the downstream tools, so they'll be
putting simulator and synthesiser options (since each user also
generates a local EDIF) into their .renoirPrefs. As far as I can see,
this is going to make regression testing and building difficult, since
the master scripts must refer to everyone's individual .renoirPrefs.
It sounds like you don't have this problem, if individual .renoirPrefs
aren't source-controlled - is this right?

My inclination is not to allow Renoir to control any downstream tools.
I can write scripts that run Renoir in batch mode just to regenerate
any VHDL, but I can't see how user X, who wants Renoir to run his
flows, can fit into an overall automated project test or build. 

>The renoir.ini (which contains the lib mappings mostly)
>is selected by setting the $RENOIRLIBS variable in each users
>environment to the same value. Changing libraries around or adding them requires
>the renoir.ini be checked out and changed by hand. This does
>not happen often, and can usually be managed in a backward 
>compatible way.
> <snipped>
>e.g.
>
>[renoir_library]
>lib_1   /source_control_file_system/$PROJECT/lib_1/renoir
>lib_2   /source_control_file_system/$PROJECT/lib_2/renoir
>
>[generated_library]
>lib_1   $USER/objects/lib_1/vhdl.gen
>lib_2   $USER/objects/lib_2/vhdl.gen
>
>[library]
>lib_1   $USER/objects/lib_1/vhdl.lib
>lib_2   $USER/objects/lib_2/vhdl.lib

It sounds like:

(a) you're keeping the working source libraries on the server, rather
than checking them out into a local directory, and 

(b) you're not keeping the generated libraries under source control,
but simply regenerating as required - is this right?

Does $RENOIRLIBS then point to a renoir.ini on the server?

It sounds like Clearcase is probably better than MKS. There's no
pre-release/release mechanism; I think I'm going to have to bodge this
by pre-releasing into an archive branch, testing, and then merging
back onto the main trunk.

Thanks

Evan


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