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Messages from 20700

Article: 20700
Subject: protocol implementations
From: "Tim Tuan" <timt@eecs.berkeley.edu>
Date: Fri, 18 Feb 2000 01:43:24 -0800
Links: << >>  << T >>  << A >>
Hi, does anyone know where I can find some sample (free) source code for
implementated protocols, such as TCI/IP, 802.11, Ethernet? For that matter,
any network related IP/cores would be very helpful.

C/C++ or HDL would be great!

-T
mailto:timtuan@yahoo.com


Article: 20701
Subject: Re: protocol implementations
From: Felix Deutsch <Felix.Deutsch@eede.ericsson.se>
Date: 18 Feb 2000 11:10:42 +0100
Links: << >>  << T >>  << A >>
"Tim Tuan" <timt@eecs.berkeley.edu> writes:

> Hi, does anyone know where I can find some sample (free) source code for
> implementated protocols, such as TCI/IP, 802.11, Ethernet? For that matter,
> any network related IP/cores would be very helpful.

Um, maybe look into the *BSD source tree.

Felix
Article: 20702
Subject: Re: RECONFIGURABLE board for image processign
From: smcc_adps@my-deja.com
Date: Fri, 18 Feb 2000 10:19:37 GMT
Links: << >>  << T >>  << A >>
Try the Optimagic web site it has links to several board vendors for
both Altera/Xilinx./

www.optimagic.com


Scott





In article <88hkr8$kn7$1@nnrp1.deja.com>,
  mrauf@nova-eng.com wrote:
> Nova Engineering has two different Altera FPGA development boards:
> Constellation and Constellation-E.  See <http://www.nova-
> eng.com/constellation.html>
>
> Both are very similar, but the "Constellation-E" adds a USB interface
> and uses the newer 10KE FPGAs from Altera
> <http://www.altera.com/html/products/f10ke.html>.  The Constellation-E
> can utilize up to an EPF10K200S.
>
> For other boards see http://www.optimagic.com/boards
>
> Michael Rauf
> Nova Engineering, Inc.
> 1.800.341.NOVA (6682)
> 1.513.860.3456
> 1.513.860.3535 (fax)
> mailto:mrauf@nova-eng.com
> http://www.nova-eng.com
> 5 Circle Freeway Drive
> Cincinnati, Ohio, USA 45246
>
> In article <38A1C9F2.9BDDD89B@dtic.ua.es>,
>   "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es> wrote:
> > Hello all,
> > I´m looking for a reconfigurable board (PCI, ISA) to develop REAL
> image
> > processing projects.
> > Any ideas?
> >
> > --
> > ===================================================================
> > Sergio A. Cuenca Asensi
> > Dept. Tecnologia Informatica y Computacion (TIC)
> > Escuela Politecnica Superior, Campus de San Vicente
> > Universidad de Alicante
> > Ap. Correos 99, E-03080 ALICANTE
> > ESPAŅA (SPAIN)
> > email   : sergio@dtic.ua.es
> > Phone : +34 96 590 39 34
> > Fax     : +34 96 590 39 02
> > ===================================================================
> >
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>

--
Alpha Data Parallel Systems
58 Timber Bush
Edinburgh
EH6 6QH


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20703
Subject: Does testability measurement play an inportant role in DFT?
From: "Jun Yang" <draggonyang@263.net>
Date: 18 Feb 2000 02:39:25 -0800
Links: << >>  << T >>  << A >>

Hi  Does testability measurement play an important 
    role in DFT? 
    If it is important,what role is played in DFT?
    What progress has been made now in testability measurement? 
Article: 20704
Subject: Interfacing multiple clock domains via FIFOs in XCV300
From: Steve Charlwood <s.m.charlwood@bham.ac.uk>
Date: Fri, 18 Feb 2000 12:31:03 +0000
Links: << >>  << T >>  << A >>
Hi...

I have a design in which I am using 32-bit synchronous FIFOs with
independent clocks to communicate between different clock domains. Due
to the limited number of block RAMs available, I am attempting to use
the same FIFO for both directions of data transfer. This means that I
need to switch the clocks at some point. This itself doesn't need to be
a fast operation, but I would like to minimise the effect on the clocks
themselves. Initially, using a simple selection (e.g. FIFO_CLK <= CLK_1
when CONDITION = TRUE else CLK_2;) Synplify would infer clock buffers
and use another two global nets, which I can't afford (I need three at
least, one for each of three primary clock domains). I avoided this by
instantiating BUFT primitives directly, but I was wondering if there was
a better way, or if anyone had experience of using so multiple clock
domains within an FPGA and had any advice.

Thanks for your help,

Steve

 
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ 

  Heterogeneous, Parallel & Reconfigurable Architectures Group 
  School of Electronic & Electrical Engineering 
  University of Birmingham, Edgbaston, Birmingham, B15 2TT 
  e-mail: s.m.charlwood@bham.ac.uk 
  tel: +44 (0)121-414-4340 (shared)/fax: +44 (0)121-414-4291 

  Signal Processing & Imagery Department 
  Defence Evaluation & Research Agency (DERA) 
  DERA Malvern, St. Andrews Road, Malvern, Worcs., WR14 3PS 
  e-mail: charlwood@signal.dera.gov.uk
  tel: +44 (0)1684-895452 (shared)/fax: +44 (0)1684-894389 

_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 20705
Subject: Re: Suggested prototyping boards < $200
From: Leon Heller <leon_heller@hotmail.com>
Date: Fri, 18 Feb 2000 13:39:09 GMT
Links: << >>  << T >>  << A >>
In article <l8Tq4.25477$Mp2.346520@typhoon2.kc.rr.com>,
  "Matt Billenstein" <mbillens@one.net> wrote:
> All, I'm interested in purchasing a prototyping board based on a
Xilinx FPGA
> and I have about $200 to spend.  I've looked a little at the boards at
> www.xess.com so far.  Does anyone have any recommendations?
>

For my own amazement, I've designed a cheap proto board for the XS05XL
(84-pin PLCC). I've had some prototypes made for my own use. Cost would
be about $50, if I put it into production. It doesn't have very much on
it -  a regulator, clock module, LED and a small prototyping area.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


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Before you buy.
Article: 20706
Subject: Re: launching a FPGA cores start-up
From: news@fkchong.freeuk.com
Date: Fri, 18 Feb 2000 13:39:38 GMT
Links: << >>  << T >>  << A >>
Interesting..


do on..


send emails to fkchong@freeuk.net


fpgaer@my-deja.com
said on Wed, 09 Feb 2000 16:24:47 GMT:
&gt; Hi,
&gt; 
&gt; wld. appreciate if anyone cld. share their views on launching a co.
&gt; which delivers custom-made FPGA cores ? Wld. the effort be worth in
&gt; terms of time ( &amp; money ) ...... specifically, is there a demanding
&gt; market for FPGA cores ???
&gt; 
&gt; Any comments wld. be highly appreciated !!!
&gt; 
&gt; Thanks in advance........
&gt; 
&gt; 
&gt; Sent via Deja.com http://www.deja.com/
&gt; Before you buy.
    
---------
Posted by fkchong - 194.168.211.198 from www.freeuk.com
Article: 20707
Subject: Re: multiplier
From: husby@fnal.gov (Don Husby)
Date: Fri, 18 Feb 2000 14:41:18 GMT
Links: << >>  << T >>  << A >>
"Keith Jasinski, Jr." <jasinski@mortara.com> wrote:
> The new FPGAs that have RAM that can be configured/initialized like a ROM
> are touting the ability to use the RAM as a single clock cycle multiplier by
> using it as a look-up table.  Maybe that might be your answer.

Also note that you can do 8-bit multiplies (or divides) in 3 cycles using
 exp(log+log).

Use one dual-port block-ram (256x9) to convert both input operands to
the log domain, use a 9-bit adder to add (or subtract), and a second
block-ram to convert back to linear.  With proper choice of the lookup
tables, you can also throw in a small constant multiplier.

Note that for maximum precision, the numbers are normalized to
a kind of floating-point format where the 8-bit ROM address represents
the fractional part of a number between 1.0 and 2.0.  If the numbers
aren't already in that format, you also need some barrel shifters.


--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406
Article: 20708
Subject: Re: coregen-bug produces bad blockram > 16 bit
From: usenet@brucke.de (Matthias Brucke)
Date: Fri, 18 Feb 2000 15:06:36 GMT
Links: << >>  << T >>  << A >>
On Thu, 17 Feb 2000 23:56:01 GMT, Ray Andraka <randraka@ids.net>
wrote:

>You still should be able to instantiate the RAMB4 primitives as a black =
box,
>no?
>

Sure.=20

But we (I work in the same departent as mark) use a construct like the
following:

In VHDL you specify the RAM as a variable  using synopsys attributes:
variable RAM is array (0 to 1024) of signed(31 downto 0);      =20
constant DataMem        : resource :=3D 0;
attribute variables     : string;
attribute variables     of DataMem  : constant is "RAM";
attribute map_to_module of DataMem  : constant is "xrams1632";

Together with that you need an .sl file containing a description of
the memory (you can write that on your own or use "memwrap")

If you schedule the RAM, synopsys uses only the .sl file but if you go
further it wants to link in the details. The easiest way is to provide
the architecture via the edif file from coregen.

An alternative would be to write a RAM-wrapper in VHDL and to
instantiate the basic building blocks for the RAM but then you would
have to bild up larger RAMS from the basic blocks on your own.=20
Coregen does this for you so it is easier to go this way.

mats

btw: we solved the problem patching the edif ;)
--
No Sig
Article: 20709
Subject: Re: coregen-bug produces bad blockram > 16 bit
From: "Mark Hillers" <Mark.Hillers@Informatik.Uni-Oldenburg.DE>
Date: Fri, 18 Feb 2000 16:02:52 +0000
Links: << >>  << T >>  << A >>
If I want use the advantage of automatic memory-access scheduling (via
map_to_module) i must not instantiate the ram as a component. In spite
of that synopsys hates black-boxes...


Ray Andraka wrote:
> 
> You still should be able to instantiate the RAMB4 primitives as a black box,
> no?
> 
> Mark Hillers wrote:
> 
> > hi jeff,
> >
> > that's not possible bacause i use the synopsys behavioral-compiler.
> > but - we could fix the problem which seems to be a language-problem
> > between coregen-edif-writer and design-compiler-edif-reader.
> >
> > fjz001@email.mot.com wrote:
> > >
> > > Mark,
> > >
> > > Why not directly instantiate the RAMB4_S16_S16 in your HDL? In this
> > > case, Coregen just adds a layer of unnecessary complexity.
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
Article: 20710
Subject: Re: Master/Serial mode for Virtex
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 18 Feb 2000 12:35:54 -0500
Links: << >>  << T >>  << A >>
Mike Peattie wrote:
> 
> Definitely a good primer on FPGA configuration.  Allow me to pick a few nits
> below:
> 
> Rickman wrote:
> > Once INIT- is high, you can start clocking the data out. The CCLK should
> > not be clocked by a free running clock. The clock edges are counted by
> > the FPGA and
> > must match the count contained within the bit file.
> >
> 
>     This is true for the 3000 and 4000 families only.  Virtex (and Spartan-II)
> do not use a LengthCount, so a free running CCLK is just fine.


Thanks for the clarification Mike. If the Virtex family does not use a
length count, how do they identify the bounds of a their bit stream?
Likewise how does a chained serial configuration work?


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20711
Subject: Re: clock
From: Sprow <rps102@york.ac.uk>
Date: Fri, 18 Feb 2000 17:35:58 +0000
Links: << >>  << T >>  << A >>


On Tue, 15 Feb 2000, Benoît HAMON wrote:

> Hi,
> 
> I'm trying to implemente (with "FOUNDATION implementation" in a Xilinx
> CPLD9500) a function in order to delay an output from an input ?.
> 
> ex : clk_out <= clk_in after 10ns.
> I found many VHDL example in Web, but never implemented.
> 
> NB: my aim is to create a Clock multiplier  : 13MHz => 26MHz.

Get some hardware on the job.Shove it through an AV9110 from Microclock
http://www.microclock.com/
None of this mamby pamby VHDL

Sprow.

> Can someone please give me an example IMPLEMENTED ?.
> 
> Please Help me !.
> Thank you in advance for your help.
> 
> benoit.hamon@elios-informatique.fr
> 
> 
> 
> 
> 
> 
> 

Article: 20712
Subject: Re: Spartan and timing analyzer: clock nets using non-dedicated
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 18 Feb 2000 12:55:06 -0500
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> 
> Tom Burgess wrote in message <38A35E12.DE1CC4F8@hia.nrc.ca>...
> >The newer parts are amazing all right. Even a slow XLA should give
> >12.5 - (1.5 Tcko + 1.5? route + 3.0 Tgls + 0.7 Tecck) = 5.8 ns margin.
> >If we were talking about ye olde 4000 series of 5+ years ago, then "worry"
> >might have been the right word.
> 
> Well, the part I'm using is a Spartan XL-4.  I've decided to not worry about
> it!

Maybe I am missing something. If you are generating a slower clock (40
MHz) from a faster clock using a divide by 2 FF, then you will have skew
between your clock domains. Signals moving from the 40 MHz domain to the
80 MHz domain will have a reduced setup time (by the amount of the
skew). This will not be easy to deal with since you are starting with
only 12.5 nS. 

But signals going from 80 MHz domain to the 40 MHz domain will have a
setup time based on the skew time, not the clock cycle time. The 40 MHz
clock edge is delayed from the 80 MHz clock edge. If you can't guaranty
that the minimum delay time for the signal is greater than the skew
time, which you can't, then you must use the skew time as your clock
cycle time for this signal! 

Am I missing something in the design? 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20713
Subject: Re: Suggested prototyping boards < $200
From: Tim Tyler <tt@cryogen.com>
Date: Fri, 18 Feb 2000 20:35:06 GMT
Links: << >>  << T >>  << A >>
John Rible <postmaster@sandpipers.com> wrote:
: Matt Billenstein wrote:

:> All, I'm interested in purchasing a prototyping board based on a Xilinx FPGA
:> and I have about $200 to spend. [...]

: Try the $150 Atmel starter kit at <http://www.kanda.com>. A bit more on the
: board than the Xess ones.

Note that there's no Xilinx FPGA on that, though.
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

Terminal error.  You're dead.
Article: 20714
Subject: Advanced Digital Design book
From: Bill Kury <wjk@datum-telegraphic.com>
Date: Fri, 18 Feb 2000 21:20:33 GMT
Links: << >>  << T >>  << A >>
Hi!  I am looking for a good reference book on advanced digital design.
The subjects that I am interested in are multiplier design,
asynchrounous state machines, etc.  If anyone has any recommmendations,
please drop me a note.

thanks

Bill


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Article: 20715
Subject: Generating a Higher Frequency Clock from a Lower One in FPGA
From: "Nestor" <nestor@ece.concordia.ca>
Date: Fri, 18 Feb 2000 21:47:01 GMT
Links: << >>  << T >>  << A >>
Hi everyone.

I am interested in building a clock synthesizer using an FPGA.  My aim is to
generate a higher frequency clock from a lower frequency reference using an
FPGA.  For instance, a 64MHz could be generated from a 1MHz reference.  In
traditional analog phase-locked loops (PLL) this is possible.  My intent is
to use a digital PLL (DPLL) or an analog-digital hybrid version of the DPLL
(everything digital except the VCO) to synthesize my higher frequency from
the lower reference.

From what I have read, a DPLL approaches its analog equivalent if the loop
is oversampled.  Does this mean that, in order to generate my 64MHz from the
1MHz, I would need to use a sampling frequency higher than 64MHz?

If this is true, then the analog PLL would be the better choice to
synthesize the 64MHz frequency since no frequency higher than 1MHz would be
required.

Thanks in advance for any suggestions or other comments.

Nestor
nestor@stansync.com
nestor@ece.concordia.ca



Article: 20716
Subject: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
From: "Nestor" <nestor@ece.concordia.ca>
Date: Fri, 18 Feb 2000 21:49:32 GMT
Links: << >>  << T >>  << A >>
Hi.

I am working on a project using Altera's FPGA FLEX10k100A-1 devices and I
would like to create a tapped delay line with a tap resolution much finer
than the my maximum operating frequency of 100MHz (10ns period).  My need
for the tapped delay line is to synchronize the phases of the different
clock nets I am using in my design.  Basically, I would like to design a
delay-locked loop (DLL) using this method.   I have heard a few months ago
that Altera's devices have a predictable interconnect delay which can be
used to create such a tapped delay.  I sent them an email a few days ago so
that they may provide me with more information regarding this topic but I
have yet to hear from them.

Anyhow, my main concerns are the following:
1)  Is it wise to use the FPGA interconnect delays to create a tapped-delay
line whose inter-tap delay would be smaller than the smallest clock
frequency period?
2)  Is there another way to implement a tapped-delay line for DLL usage
using an FPGA?

Thanks in advance to everyone who can provide suggestions and comments on
the above.

Nestor
nestor@stansync.com
nestor@ece.concordia.ca



Article: 20717
Subject: Re: Logiblox and virtex
From: Alfred Rodriguez <arodrigu@xilinx.com>
Date: Fri, 18 Feb 2000 14:50:00 -0700
Links: << >>  << T >>  << A >>
Federico Silla wrote:

> Hi everybody,
>
> I am trying to get started with the fpga design on a Virtex. Up to now, I
> have designed my circuits with the Xilinx 4000 family, using logiblox when
> needed. However, when I have moved to Virtex, I have realized that the
> software tool Foundation (verion 2.1i) does not allow to design logiblox for
> virtex. Does anybody know where have logiblox gone? Does anyone know how to
> use some other design tool instead of logiblox?
>
> Thanks in advance
>
> Federico Silla

The Coregen tool will allow you to target a Virtex.  Logiblox doesn't
support any Virtex designs.  You should also get the updates to the Coregen
tool at the support.xilinx.com site.

Regards,
Alfred

Article: 20718
Subject: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
From: Ray Andraka <randraka@ids.net>
Date: Fri, 18 Feb 2000 23:04:57 GMT
Links: << >>  << T >>  << A >>
You can get finer resolution using the carry chain as a tapped delay line.
Selecting the taps with a multiplexer is somewhat problematic because the
interconnect delay to the selector has to be equal for all taps for it to work
right.  You will probably get considerably better results by fixing the delay
output at one point on the carry chain and then using the carry chain gates to
select where on the carry chain the input clock is inserted.  You will have to
be clever to get the different phases out.  The input clock, being from the
global clock net with identical routes from the global clock network to the
carry chain input logic.  I think you will have better luck with xilinx because
you have more control over the routing there.  With Altera, the route is only
predictable as long as you know what resources you are going through.  You can
wind up with longer than anticipated routes within a row if you try to connect
LABs that do not have a direct connection between them (ie you need to route
through a third lab to get there).  This becomes an issue if the row route
utilization is more than about 40-50% or if you direct placement without regard
to the row route connections (the row route resource is a sparse connection
matrix).  Unfortunately, the tools hide a lot of this detail from the user.

The xilinx has unfairly earned a reputation for not having a predictable
routing delay.  That is a result of designs being put in without any
placement/routing constraints.  The xilinx delays are in fact deterministic,
but are more sensitive to placement, especially haphazard placement.  For a
DLL, no matter what device you use, you will want to get in and do at a minimum
hand placement regardless of your choice of device.  The Xilinx tools give you
much more visibility and controllability at the level of detail you will need
to be successful on a DLL design.

Nestor wrote:

> Hi.
>
> I am working on a project using Altera's FPGA FLEX10k100A-1 devices and I
> would like to create a tapped delay line with a tap resolution much finer
> than the my maximum operating frequency of 100MHz (10ns period).  My need
> for the tapped delay line is to synchronize the phases of the different
> clock nets I am using in my design.  Basically, I would like to design a
> delay-locked loop (DLL) using this method.   I have heard a few months ago
> that Altera's devices have a predictable interconnect delay which can be
> used to create such a tapped delay.  I sent them an email a few days ago so
> that they may provide me with more information regarding this topic but I
> have yet to hear from them.
>
> Anyhow, my main concerns are the following:
> 1)  Is it wise to use the FPGA interconnect delays to create a tapped-delay
> line whose inter-tap delay would be smaller than the smallest clock
> frequency period?
> 2)  Is there another way to implement a tapped-delay line for DLL usage
> using an FPGA?
>
> Thanks in advance to everyone who can provide suggestions and comments on
> the above.
>
> Nestor
> nestor@stansync.com
> nestor@ece.concordia.ca

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20719
Subject: BEHAVIOURAL VHDL
From: ritchie99_uk@my-deja.com
Date: Fri, 18 Feb 2000 23:06:04 GMT
Links: << >>  << T >>  << A >>
HI ALL,

what's the performance of the actual synthesisers for a behavioural
vhdl input
i am looking to target the VIRTEX-E with a behavioural vhdl input, and
here i don't know  which synthesiser(s) is (are) good especially for
inferring Block Rams and distributed RAMs

i read that "exemplar" infers automatically the BRAM , what about FPGA
express that come with F2.1i, is it good  ???
same question for synplify and symplicity ( i hope that it's the right
spelling ...)

thanks in anticipation

--ritchie


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Article: 20720
Subject: Re: protocol implementations
From: stanislav shalunov <shalunov@att.com>
Date: Sat, 19 Feb 2000 01:29:18 GMT
Links: << >>  << T >>  << A >>
"Tim Tuan" <timt@eecs.berkeley.edu> writes:

> Hi, does anyone know where I can find some sample (free) source code
> for implementated protocols

You're at Berkeley, why do you ask us?
Grab FreeBSD's /usr/src/sys/net* or something.
Article: 20721
Subject: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 18 Feb 2000 18:20:54 -0800
Links: << >>  << T >>  << A >>
Although we all try hard to keep this newsgroup free of blatantly commercial
messages, I cannot help to ask:
Why do you not consider Xilinx Virtex, where there are 4 to 8 ready-made
delay-locked loops, each with 35 ps granularity, that seem to do exactly what
you want done. Why "re-invent the wheel", with unavoidably much coarser
granularity, and all sorts of implementation trouble ?

Peter Alfke, Xilinx Applications
================================
Nestor wrote:

> Hi.
>
> I am working on a project using Altera's FPGA FLEX10k100A-1 devices and I
> would like to create a tapped delay line with a tap resolution much finer
> than the my maximum operating frequency of 100MHz (10ns period).  My need
> for the tapped delay line is to synchronize the phases of the different
> clock nets I am using in my design.  Basically, I would like to design a
> delay-locked loop (DLL) using this method.   I have heard a few months ago
> that Altera's devices have a predictable interconnect delay which can be
> used to create such a tapped delay.  I sent them an email a few days ago so
> that they may provide me with more information regarding this topic but I
> have yet to hear from them.
>
> Anyhow, my main concerns are the following:
> 1)  Is it wise to use the FPGA interconnect delays to create a tapped-delay
> line whose inter-tap delay would be smaller than the smallest clock
> frequency period?
> 2)  Is there another way to implement a tapped-delay line for DLL usage
> using an FPGA?
>
> Thanks in advance to everyone who can provide suggestions and comments on
> the above.
>
> Nestor
> nestor@stansync.com
> nestor@ece.concordia.ca

Article: 20722
Subject: Xilinx 9500 CPLD
From: "Tim Tuan" <timt@eecs.berkeley.edu>
Date: Fri, 18 Feb 2000 18:35:42 -0800
Links: << >>  << T >>  << A >>
Hi, why doesn't Xilinx make their 9500 CPLDs any larger. What's the
constraining factor?

Thanks,
-T
mailto:timtuan@yahoo.com


Article: 20723
Subject: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
From: nestor@stansync.com
Date: Sat, 19 Feb 2000 04:04:21 GMT
Links: << >>  << T >>  << A >>
Thanks for your reply.

I am aware that xilinx has introduced the DLLs in their virtex series
with many more advantages such as hardwired multipliers, but I am
unfortunately stuck using altera for my current design.  Possibly when
the design size becomes too large I will switch over to xilinx .

Nestor

--

On Fri, 18 Feb 2000 18:20:54 -0800, Peter Alfke <peter@xilinx.com>
wrote:

>Although we all try hard to keep this newsgroup free of blatantly commercial
>messages, I cannot help to ask:
>Why do you not consider Xilinx Virtex, where there are 4 to 8 ready-made
>delay-locked loops, each with 35 ps granularity, that seem to do exactly what
>you want done. Why "re-invent the wheel", with unavoidably much coarser
>granularity, and all sorts of implementation trouble ?
>
>Peter Alfke, Xilinx Applications
>================================


Article: 20724
Subject: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
From: nestor@stansync.com
Date: Sat, 19 Feb 2000 04:16:50 GMT
Links: << >>  << T >>  << A >>
Thanks for your suggestion.  

For the time being I am using altera and I cannot switch to xilinx yet
although xilinx offers some nice features in their virtex series as
well as in their cores such as the fir...

>You can get finer resolution using the carry chain as a tapped delay line.
>Selecting the taps with a multiplexer is somewhat problematic because the
>interconnect delay to the selector has to be equal for all taps for it to work
>right.  You will probably get considerably better results by fixing the delay
>output at one point on the carry chain and then using the carry chain gates to
>select where on the carry chain the input clock is inserted.  You will have to
>be clever to get the different phases out.  The input clock, being from the
>global clock net with identical routes from the global clock network to the
>carry chain input logic.  I think you will have better luck with xilinx because
>you have more control over the routing there.  With Altera, the route is only
>predictable as long as you know what resources you are going through.  You can
>wind up with longer than anticipated routes within a row if you try to connect
>LABs that do not have a direct connection between them (ie you need to route
>through a third lab to get there).  This becomes an issue if the row route
>utilization is more than about 40-50% or if you direct placement without regard
>to the row route connections (the row route resource is a sparse connection
>matrix).  Unfortunately, the tools hide a lot of this detail from the user.

I do like xilinx's full control over the constraints, not only the
clock requirements but also the ability to organize the layout of the
placement down to the lower CLB level.  My previous experience with
xilinx has been very good and only recently I have started using
altera because the board I am working on uses those parts.

>
>The xilinx has unfairly earned a reputation for not having a predictable
>routing delay.  That is a result of designs being put in without any
>placement/routing constraints.  The xilinx delays are in fact deterministic,
>but are more sensitive to placement, especially haphazard placement.  For a
>DLL, no matter what device you use, you will want to get in and do at a minimum
>hand placement regardless of your choice of device.  The Xilinx tools give you
>much more visibility and controllability at the level of detail you will need
>to be successful on a DLL design.
>


Nestor


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