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# Messages from 20975

Article: 20975
From: Tom Leacock <tom@pavcal.com>
Date: Wed, 01 Mar 2000 15:30:18 -0500
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Can anyone give any feedback of how many virtex loads ( each on a different
chip)&nbsp; can be driven with one virtex output, either in a terminated
daisy chained transmission line or a distributed bus to 6 devices? The
data bus is running at 80 Mhz.
<br>Thanks,
<br>-Tom
<br>----------------------------------------------
<br>Thomas Leacock
<br>Panasonic AVC American Laboratories (PAVCAL)
<br>95 D Connecticut Dr.
<br>Burlington NJ 08016-4180
<p>Phone: 609-386-8600 ext.115
<br>Fax:&nbsp;&nbsp; 609-386-4999
<p>email: toml@pavcal.com
<br>----------------------------------------------
<br>&nbsp;</html>


Article: 20976
Subject: Re: Xilinx Tools Vs Altera tools
From: Ray Andraka <randraka@ids.net>
Date: Wed, 01 Mar 2000 21:18:30 GMT
Links: << >>  << T >>  << A >>
Your 'best' target is going to depend on what kind of design you are doing.  If it
is a DSP design, one that uses lots of arithmetic, is heavily data path or requires
many small delay queues (like in a filter) then you'll want to use a Xilinx part.
You'll get much better utilization and with a little bit of floorplanning will
significantly outperform an Altera device.  On the otherhand, if you are gathering
lots of random logic or have large state machines, Altera might fare better.

If you floorplan in xilinx, the M2.1 tools will generally do a place and route in
less than 2 hours, depending on the size of the device and complexity of the
design.  I've got a 133 MHz XCV1000 design here that takes about 45 minutes through
the PAR with about half of the design floorplanned. Xilinx has good support for
incremental designs, and the timing driven place and route works well.  The
placement algorithm does not do a very good job; a little floorplanning can
drastically improve the design fmax.

For Altera, the current release is MaxplusII v9.4.  The timing driven route in that
does not do very well and takes a very long time doing it.  You are better off
turning the timing driven part off and going with luck of the draw.  You will find
that the larger the device the slower the speeds in Altera (which is not the case
with Xilinx)...just something to be aware of.  The next release, v9.5 is much
faster and the timing driven place and route seems to work as it is supposed to.
I think that is supposed to ship within the next few weeks.   A 10K250 design I
recently completed took about 8 hours through PAR with the timing turned off, but
did not meet timing in the 9.4 tools.  Under 9.5, that design completes in about 2
hours.  It is a 65% utilized 10K250.

Jerry English wrote:

> Glad this thread started. I too am looking at Altera/Xilinx for a large design,
> gates. What that equates to in fpga gates is up for debate. What I want to know
> is what kind of
> time am I looking at as far as place and routes go,. When I make small changes
> in the design do I
> have to start from "bare die" or can the existing layout be modified? Since it
> appears that Synopsys's
> FPGA express is the front end tool for HDL what kind of times should one expect
> for compiling?
> If you do respond please indicate the platform.
>
> Thanks
> Jerry
>
> wamsi@my-deja.com wrote:
>
> > How does Quartus for APEX compare with the Xilinx tools version for Virtex.
> > Principally I am interested in post Synopsys features.
> > 1. Timing analysis reports
> > 2. Fitter/Router
> > 3. any experience with compile time for 1mil gate designs
> > 4. timing driven compilation
> > 5. Incremental compile
> > 6. Testability tools
> >
> > Thanks
> > -Wamsi
> >
> > Sent via Deja.com http://www.deja.com/

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20977
Subject: Re: Philips LA PM3585 disassembler software wanted
From: z80@ds2.com (Peter)
Date: Wed, 01 Mar 2000 22:37:48 +0000
Links: << >>  << T >>  << A >>

>Today (Feb. 2000) there is no support neither from Philips nor from Fluke.
>I asked them both, but they told that they have physically shreddered all
>parts for this product?!

What could possibly be the reason for this bizzare behaviour?

Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.


Article: 20978
Subject: Re: Xilinx PCI pinout ?
From: "Steve Casselman" <sc@vcc.com>
Date: Wed, 1 Mar 2000 16:44:58 -0800
Links: << >>  << T >>  << A >>
I think the memec group can help on this.
pci@memecdesign.com

Steve Casselman, President
Virtual Computer Corporation


Article: 20979
From: javidiaz@my-deja.com
Date: Thu, 02 Mar 2000 03:38:18 GMT
Links: << >>  << T >>  << A >>
Thanks guys for your comment on my AMS questions!

Just to get some feedback...

I am designing (on the same AMS board) a image processing algorithm. It
can be divided in five stages. The general description is as follows:
1. the system got a 8x8 image sample (@8 bits)
2. it is applied 6 convolution filters to the same sample; getting 6
outputs (1st stage)
3. then to each of those 6 matrices( previous outputs) a "standard
deviation" matrix is generated (2nd stage)
4. to each of 2nd stage outputs, 4 different "zonal mask" are applied
generating 24 byte outputs, i.e., each SD matrix is transformed to 4
bytes (3rd stage)
5. The "normalization" is applied to the whole vector 24x1 (Ri=Ei/Max
(Ei)) (4rd stage)
6. A sort is applied to the normalized vector based on statistical
measures (mean & standard-deviation) (5 stage)

My doubts are:
a. So far this design will require a buuuunch of routing resources. I
am trying to avoid serial processing as much as possible (except when
entering the data to stage 1) Do I am dreaming?!
b. For me calculating the standard-deviation is creating two issues:
1. not integer numbers, i.e., decimal digits (which they will be
carried through every subsequent stage)
2. time (peeking every byte) wasting and H/W (square root,
multipliers, accumulators) expenditure.
c. Which number representation will be less troublesome to implement
from
stage 2 to stage 5 , fix-point or floating-point?
d. I will try to partition the design between two PEs: XC4036XLA and
XC4013XLA. Any partitioning advice? (I have some ideas we can discuss
them...)

I have the willingness to enter to this fascinating technological

Javier University of PR

Sent via Deja.com http://www.deja.com/

Article: 20980
Date: Thu, 02 Mar 2000 05:49:11 GMT
Links: << >>  << T >>  << A >>
If you want to be precise, use the IBIS files that describe the output
current/voltage characteristics for the different output options.

For a rough guess, look at page 14-64/65 in the Xilinx 99 data book.

We might agree on an output impedance of 20 Ohm.
If you are willing to sacrifice 5 ns extra delay for the loading effect,
you can drive 250 pF  ( 250 pF x 20 Ohm = 5 ns ). Each input is about 10
pF, disregarding the pc-board trace.

Page 14-16 of the data book gives ~ 1.5 ns per 100 pF, which is pretty
close.

That is looking at the load as a lumped capacitance, which it obviously
is not, but it gives you a feel for the drive capability.
For an accurate answer, one would need to know much more about your
layout.

Peter Alfke, Xilinx Applications

Tom Leacock wrote:

> Can anyone give any feedback of how many virtex loads ( each on a
> different chip)  can be driven with one virtex output, either in a
> terminated daisy chained transmission line or a distributed bus to 6
> devices? The data bus is running at 80 Mhz.
> Thanks,
> -Tom
> ----------------------------------------------
> Thomas Leacock
> Panasonic AVC American Laboratories (PAVCAL)
> 95 D Connecticut Dr.
> Burlington NJ 08016-4180
>
> Phone: 609-386-8600 ext.115
> Fax:   609-386-4999
>
> email: toml@pavcal.com
> ----------------------------------------------
>


Article: 20981
Subject: Re: Extremely fault tolerant strategies
From: Philip Koopman <koopman@cmu.edu>
Date: Wed, 01 Mar 2000 23:23:34 -0800
Links: << >>  << T >>  << A >>
Greg Deych <gdeych@my-deja.com> wrote:

>Does anybody know of a resource (web, book or article) describing
>architecture design for systems, storage or logic, whose components
>are prone to very high rate of failure, along the line of 0.1%-1%?

You'd really need to express that failure rate in terms of failures per
unit time and then contrast that to expected "mission time".

Do you mean failures of 1% per hour?  How long until you get to repair
it -- 1 hours or 10,000 hours?

The usual tool to deal with this is redundancy, and there are shelves
and shelves of books that deal with that.  But it only works for
"moderate" failure rates with a lot of caveats and a lot of money in
many cases.

-- Phil

Phil Koopman -- koopman@cmu.edu -- http://www.ices.cmu.edu/koopman


Article: 20982
Subject: Re: Xilinx Tools Vs Altera tools
From: "Bob Baman" <bbauman@lynxstudio.com>
Date: Thu, 02 Mar 2000 08:22:40 GMT
Links: << >>  << T >>  << A >>
Ray,

Since you are in the subject of optimization, how is fmax affected for
better or worse by FPGA Express versus Synplify synthesis?

Ray Andraka <randraka@ids.net> wrote in message
news:38BD8908.82EC604@ids.net...
> Your 'best' target is going to depend on what kind of design you are
doing.  If it
> is a DSP design, one that uses lots of arithmetic, is heavily data path or
requires
> many small delay queues (like in a filter) then you'll want to use a
Xilinx part.
> You'll get much better utilization and with a little bit of floorplanning
will
> significantly outperform an Altera device.  On the otherhand, if you are
gathering
> lots of random logic or have large state machines, Altera might fare
better.
>
> If you floorplan in xilinx, the M2.1 tools will generally do a place and
route in
> less than 2 hours, depending on the size of the device and complexity of
the
> design.  I've got a 133 MHz XCV1000 design here that takes about 45
minutes through
> the PAR with about half of the design floorplanned. Xilinx has good
support for
> incremental designs, and the timing driven place and route works well.
The
> placement algorithm does not do a very good job; a little floorplanning
can
> drastically improve the design fmax.
>
> For Altera, the current release is MaxplusII v9.4.  The timing driven
route in that
> does not do very well and takes a very long time doing it.  You are better
off
> turning the timing driven part off and going with luck of the draw.  You
will find
> that the larger the device the slower the speeds in Altera (which is not
the case
> with Xilinx)...just something to be aware of.  The next release, v9.5 is
much
> faster and the timing driven place and route seems to work as it is
supposed to.
> I think that is supposed to ship within the next few weeks.   A 10K250
design I
> recently completed took about 8 hours through PAR with the timing turned
off, but
> did not meet timing in the 9.4 tools.  Under 9.5, that design completes in
> hours.  It is a 65% utilized 10K250.
>
>
>
> Jerry English wrote:
>
> > Glad this thread started. I too am looking at Altera/Xilinx for a large
design,
> > about half million ASIC
> > gates. What that equates to in fpga gates is up for debate. What I want
to know
> > is what kind of
> > time am I looking at as far as place and routes go,. When I make small
changes
> > in the design do I
> > have to start from "bare die" or can the existing layout be modified?
Since it
> > appears that Synopsys's
> > FPGA express is the front end tool for HDL what kind of times should one
expect
> > for compiling?
> > If you do respond please indicate the platform.
> >
> > Thanks
> > Jerry
> >
> > wamsi@my-deja.com wrote:
> >
> > > How does Quartus for APEX compare with the Xilinx tools version for
Virtex.
> > > Principally I am interested in post Synopsys features.
> > > 1. Timing analysis reports
> > > 2. Fitter/Router
> > > 3. any experience with compile time for 1mil gate designs
> > > 4. timing driven compilation
> > > 5. Incremental compile
> > > 6. Testability tools
> > >
> > > Thanks
> > > -Wamsi
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>
>


Article: 20983
Subject: Re: Bit Serial Arithmetic De-mystified
From: jg.campbell <jg.campbell@qub.ac.uk>
Date: Thu, 02 Mar 2000 10:29:12 GMT
Links: << >>  << T >>  << A >>
In article <38B38480.5F39CC48@ieee.org>,
jyavins@erols.com wrote:
> "E. Robert Tisdale" wrote:
> >
> > What the heck is bit serial arithmetic?
>
> Try to find documentation on the PDP8S. That was a bit serial machine.
> Some old IC logic books have spec sheets for bit serial adders.

Hmmm... we assumed that the S stood for Slow ... now I know why (it was
so slow ;-)

Best regards,

Jon Campbell

--
Jonathan G. Campbell, School of Computer Science, The Queen's University
of Belfast, BT7 1NN  Tel +44 028 90 274623  jg.campbell@qub.ac.uk
http://www.cs.qub.ac.uk/~J.Campbell

Sent via Deja.com http://www.deja.com/


Article: 20984
Subject: Re: Xilinx Tools Vs Altera tools
From: "David Hawke" <dhawke@skynow.net>
Date: Thu, 2 Mar 2000 10:36:48 -0000
Links: << >>  << T >>  << A >>
Compile time depends on a number of things...

Design speed, Logic levels, PC memory.
I have a number of designs (all datapath and control based) in V1000's that
running at upto 75MHz
take upto 1hr (>70% utilisation) on a PIII 500, with 512MB RAM.

I have one design that went ASIC and as the design had been done to take
advantage of the SRL16's in Virtex
it suddenly exploded to >50,000 D types...

At to interative design, it is very difficult and error prone to do with
Synthesis tools, due to net renaming etc.
The only one that I have used successfully to do this is Leonardo.
Synopsys may be OK, as they are getting better at net name preservasion...

D.
Jerry English wrote in message <38BD7359.D070F079@planetc.com>...
>Glad this thread started. I too am looking at Altera/Xilinx for a large
design,
>gates. What that equates to in fpga gates is up for debate. What I want to
know
>is what kind of
>time am I looking at as far as place and routes go,. When I make small
changes
>in the design do I
>have to start from "bare die" or can the existing layout be modified? Since
it
>appears that Synopsys's
>FPGA express is the front end tool for HDL what kind of times should one
expect
>for compiling?
>If you do respond please indicate the platform.
>
>Thanks
>Jerry
>
>wamsi@my-deja.com wrote:
>
>> How does Quartus for APEX compare with the Xilinx tools version for
Virtex.
>> Principally I am interested in post Synopsys features.
>> 1. Timing analysis reports
>> 2. Fitter/Router
>> 3. any experience with compile time for 1mil gate designs
>> 4. timing driven compilation
>> 5. Incremental compile
>> 6. Testability tools
>>
>> Thanks
>> -Wamsi
>>
>> Sent via Deja.com http://www.deja.com/
>


Article: 20985
Subject: Re: Extremely fault tolerant strategies
Date: Thu, 2 Mar 2000 10:44:04 -0000
Links: << >>  << T >>  << A >>
take a look at

http://www.amp.york.ac.uk/external/media/cal/welcome.html

bits of 'something a bit different' on fault tolerant design

Greg Deych <gdeych@my-deja.com> wrote in message
news:puambss4b4iuvdsu54rgiu6jb86tthne5n@4ax.com...
> Does anybody know of a resource (web, book or article) describing
> architecture design for systems, storage or logic, whose components
> are prone to very high rate of failure, along the line of 0.1%-1%?


Article: 20986
Subject: Re: Comment on Atmel AT40K ?
From: "Ulf Samuelsson" <ulf.samuelsson@atmel.spamme.com.not>
Date: Thu, 2 Mar 2000 13:00:00 +0100
Links: << >>  << T >>  << A >>
Can't say I am unbiased, but the embedded RAM makes it interesting for
many communications applications. This, the possibility to
update on the fly, together with the new FPSLIC with embedded AVR
is what makes people most interested.
Figaro is still around but you can use many other tools.
PCs are much faster nowadays which makes life easier.
With todays, delivery situations, the fact that they are pin compatible
to some Xilinx devices should also not be underestimated.

To try out the AT40K , the Kanda Systems devboard is available at an
attractive price. www.kanda-systems.com

--
This is a personal view which may or may not be shared
by my employer         Atmel Sweden
Ulf Samuelsson         ulf 'a't atmel 'd'o't com

Ray Andraka skrev i meddelandet <38BF11A7.6260B9E4@ids.net>...
>My stock answer:  It depends on the application.
>
>The 40K's Achilles heel is the fact it has no fast carry logic.  That
really
>cripples its arithmetic performance/density when compared to Xilinx.  If
you
>don't need a carry chain (unfortunately, I can only think of a few
>applications that don't benefit there), it's not all that bad a device.  I
>truthfully have not looked at their software in a few years.  I would hope
>that it has been improved.  Previously they were using Figaro, which was
>dreadfully slow, especially when you tried to do any edits.  I think they
>still give away the software for free.  You might test drive it to see what
>you think.
>
>Peter Fenn wrote:
>
>> Hi
>> I am looking for 1st-hand comment from users of Atmel AT40K FPGA tools
and
>> devices.
>> - What are the shortcomings?
>> - How does it compare to eg. Xilinx?
>> - How does architecture rate compared to other FPGA offerings out there?
>> - What is the "sweet-spot" in terms of price, performance,etc?
>> - Any other observations / tips appreciated
>>
>> Thanks for all your input
>> Pete Fenn
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>


Article: 20987
Subject: Re: PCI Core Problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 02 Mar 2000 08:38:19 -0500
Links: << >>  << T >>  << A >>
Antonio Joaquim A Esteves wrote:
>
> Hello,
>
> We designed a prototyping board with Xilinx FPGAs and a PCI
> interface implemented with the Xilinx LogiCORE 2.0.2 (slave
> only) and a 4013XLT device.
>
> The board has been used, but a problem remain unsolved:
>
> "on faster PCs and/or when using optimized s/w to implement
> read/write operations that access the FPGAs, these operations
> seem not to succeed and in some situations the operating
> system (OS) hangs up".
>
> What makes the OS to hang up when executing a sequence of
> "a writing operation (to send a FPGA configuration
> byte) followed by a read operation (to read FPGA status)" with
> optimized code ?
> The interrupt signal seems not to be asserted ...
>
> Since h/w logic adds long delays, we decided to deassert SREADY
> signal for one state during read operations. Can this cause problems ?
>
> Any ideas will be apreciated.
> Regards.
>
>  -----------------------------------------------------
>  Antonio J A Esteves
>  Departamento de Informatica - Universidade do Minho
>  Largo do Paco - 400-320 Braga Codex - Portugal
>
>  Phone:  +351 253 604454  Fax: +351 253 604471
>  E-mail: esteves@di.uminho.pt
>  Web:    http://www.di.uminho.pt/~esteves/
>  -----------------------------------------------------

We saw hangups on a board we were designing when the target inboard
logic did not respond to the PCI interface. I don't know exactly what
would appear on the PCI bus, but it seems that the bus master did not
time out waiting for a response. So the OS would hang so hard, that even
the reset button did not work! We would have to cycle power to get the
machine out of lockup. The fix in our case was to identify the bug that
kept the logic from responding.

--

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


Article: 20988
Subject: Re: JTAG Programmer & Windows 2000
From: Edward Lee <edlee@seidcon.com>
Date: Thu, 02 Mar 2000 06:28:45 -0800
Links: << >>  << T >>  << A >>
Can I use a simpler Jtag cable than the one suggested in Xilinx's web?
Xilinx's cable requires lot of buffers and resistors, which would make the
ISP PCB bigger and more expensive.  By the way, I have been programming
Vantis/Mach CPLD's with straight wires from the parallel port.   I am
exploring alternative because Vantis/Mach prices went up quite a bit since
Lattice brought it from AMD.

Robert Binkley wrote:

> Yes.  JTAG Programmer runs on Windows 2000 even though the release notes
> do not say anything about it.  Installing the WebPack2.1iwp5.x JTAG
> successfully programmed:
>
>      XC9536XL
>      XCV50
>
> through the following cables:
>
>      Parallel Cable III
>      MultiLINX-Serial
>
> If you are getting a software error, I suggest you open a web support
> case with the hotline at:  http://support.xilinx.com
>
> Sincerely,
>
> Robert Binkley
> Xilinx Applications
>
> Andrew McCartney wrote:
>
> > Has anyone used the Xilinx JTAG Programmer SW and the Parallel Cable
> > III with Windows 2000? I have installed and used the Fndtn 2.1i tools
> > under 2000, but I cannot get the JTAG Programmer to work properly.


Article: 20989
Subject: Re: Extremely fault tolerant strategies
From: Mark W Brehob <brehob@cse.msu.edu>
Date: 2 Mar 2000 15:06:49 GMT
Links: << >>  << T >>  << A >>
In comp.arch Greg Deych <gdeych@my-deja.com> wrote:
> Does anybody know of a resource (web, book or article) describing
> architecture design for systems, storage or logic, whose components
> are prone to very high rate of failure, along the line of 0.1%-1%?

This might be well known to those of you in the fpga world:

"A defect-tolerant Computer Architecure: Opportunities for
Nanotechnology" J. Heath, P. Juekes, G. Snider, R. Williams. Science, 12
June 1998, pages 1716-1721.

Note it is _defect_ tolerant, not fault tolerant per se.  That is it finds
the errors in the system _then_ starts to do work.  It assumes that it is
working with highly-broken components, but that they aren't in the process
of breaking as time goes on.

Mark

--
~~~~~~~~~~~~~~~~ http://www.cps.msu.edu/~brehob ~~~~~~~~~~~~~~~~~~
~~~~~~Mark Brehob: Ultimate Player, Gamer, Computer Geek~~~~~~~~~~


Article: 20990
Subject: Re: Xilinx Tools Vs Altera tools
From: Ray Andraka <randraka@ids.net>
Date: Thu, 02 Mar 2000 15:38:15 GMT
Links: << >>  << T >>  << A >>
Depends on how you code it :-)

Bob Baman wrote:

> Ray,
>
> Since you are in the subject of optimization, how is fmax affected for
> better or worse by FPGA Express versus Synplify synthesis?
>
> Ra

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20991
From: Ray Andraka <randraka@ids.net>
Date: Thu, 02 Mar 2000 15:40:34 GMT
Links: << >>  << T >>  << A >>
You didn't say what your pixel rate is.  It makes a difference.

javidiaz@my-deja.com wrote:

> Thanks guys for your comment on my AMS questions!
>
> Just to get some feedback...
>
> I am designing (on the same AMS board) a image processing algorithm. It
> can be divided in five stages. The general description is as follows:
> 1. the system got a 8x8 image sample (@8 bits)
> 2. it is applied 6 convolution filters to the same sample; getting 6
> outputs (1st stage)
> 3. then to each of those 6 matrices( previous outputs) a "standard
> deviation" matrix is generated (2nd stage)
> 4. to each of 2nd stage outputs, 4 different "zonal mask" are applied
> generating 24 byte outputs, i.e., each SD matrix is transformed to 4
> bytes (3rd stage)
> 5. The "normalization" is applied to the whole vector 24x1 (Ri=Ei/Max
> (Ei)) (4rd stage)
> 6. A sort is applied to the normalized vector based on statistical
> measures (mean & standard-deviation) (5 stage)
>
> My doubts are:
> a. So far this design will require a buuuunch of routing resources. I
> am trying to avoid serial processing as much as possible (except when
> entering the data to stage 1) Do I am dreaming?!
> b. For me calculating the standard-deviation is creating two issues:
>    1. not integer numbers, i.e., decimal digits (which they will be
> carried through every subsequent stage)
>    2. time (peeking every byte) wasting and H/W (square root,
> multipliers, accumulators) expenditure.
> c. Which number representation will be less troublesome to implement
> from
> stage 2 to stage 5 , fix-point or floating-point?
> d. I will try to partition the design between two PEs: XC4036XLA and
> XC4013XLA. Any partitioning advice? (I have some ideas we can discuss
> them...)
>
> I have the willingness to enter to this fascinating technological
>
> Javier University of PR
>
> Sent via Deja.com http://www.deja.com/

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20992
Subject: Re: Extremely fault tolerant strategies
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Thu, 02 Mar 2000 15:49:47 +0000
Links: << >>  << T >>  << A >>
On Tue, 29 Feb 2000 02:20:41 GMT, Greg Deych <gdeych@my-deja.com> wrote:

>Does anybody know of a resource (web, book or article) describing
>architecture design for systems, storage or logic, whose components
>are prone to very high rate of failure, along the line of 0.1%-1%?

I wonder if it's worth trawling for information from the vacuum-tube and
mercury delay line days (ACE, EDSAC, LEO etc), the late 40's and very
early 50's. They faced these problems and usually, certainly LEO (Lyons
Electronic Office) did, developed strategies to deal with them ... e.g.
regular checkpointing, running test patterns with over/under voltage to
catch marginal performance, etc.

As a start I'd search for M.V. (Maurice) Wilkes and see what turns up...

- Brian


Article: 20993
Subject: ORCA 3T - input/output delay reduction?
From: Harald Simmler <simmler@ti.uni-mannheim.de>
Date: Thu, 02 Mar 2000 18:19:48 +0100
Links: << >>  << T >>  << A >>
Hi

I have a design where 4 ORCA 3T125  chips communicate together
( programmed in VHDL ). All four designs should run at arond 20 MHz.
At least the P&R tools calculates that frequency on internal delays.

But the highest frequency on the board is only 8MHz.
The FPGAs are directly connected by wires, so I think that this
should not be the problem. I think that the PIO blocks which are
programmed as input add an delay block at the
input ( per default ? ) which has to be added to the internal
tPD. And the output is set to slow ( also per default ? ).

Has anyone an idea what reduces the frequency and does anyone
know how to disable the input delay or change the settings for the PIO
blocks during P&R ( constrains  in the CHDL code or in a constrains file
)??

Any help is needed.

H. Simmler

--

---------------------------------------------------------------------------
Harald Simmler                               Lehrstuhl fuer Informatik V
Universitaet Mannheim
Tel:    +49-621-181-2632   ! NEW !           B6, 26
Fax:    +49-621-181-2634   ! NEW !           D-68131 Mannheim
eMail:   simmler@ti.uni-mannheim.de          Germany

Article: 20994
Subject: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 2 Mar 2000 11:32:27 -0700
Links: << >>  << T >>  << A >>
Gary Cook wrote in message <38B4E75D.CAA624D7@sonyoxford.co.uk>...

>"On-Line" arithmetic is a new form of arithmetic being tested at MIT
>I believe ... instead of writing complex and space consuming
>algorithms within FPGAs for functions such as sin/cos etc., the
>FPGA has a state machine that is programmed to generate ethernet
>packets that can be transmitted over the internet. They are sent,
>through an internet connection that the FPGA has access to, to a
>server somewhere that has enough grunts to be able to perform the
>requested arithmetic function very very quickly ... the result is returned
>back to the FPGA within a maximum time, but which is significantly
>less than the time it would have taken the fpga to perform it. In this
>way it is easy to envisage even more complex arithmetic functions
>being implemented, that have a deterministic response time.
>Of course, the server will typically only be performing arithmetic
>tasks, but if it's powerful enough it could serve many FPGA's
>thoeretically anywhere in the world ... even from space! It is
>possible, however, that due to internet congestion or packet
>misdirection, that the result that the FPGA is returned is not
>the expected arithmetic result, but the 1-800 telephone number of
>Delicous Debby Daring to Dabble in Delightful Doings .. rather
>confusing for the poor FPGA I wager ....
>
>... at least that's what I read in Electronics Times....

sounds like a clever method of extracting money from not-so-clever VCs!

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
-- Justice John Paul Stevens


Article: 20995
Subject: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
From: z80@ds2.com (Peter)
Date: Thu, 02 Mar 2000 18:56:47 +0000
Links: << >>  << T >>  << A >>

>I would go for Xilinx Foundation with FPGA Express - it won't cost
>anything like $15k. Also, I don't agree that Foundation 2.1i (with service >pack 5) >is really 'buggy'. I have a licensed copy in the office of versions 1.3 and 1.4 of the Xilinx successor to XACT, but at this moment can't remember its name - damn! Xilinx did a freebie on these to all XACT6 licensees. I wonder if this is relevant. I think it contains a primitive schematic entry program and maybe even a simulator. It locks to the C: drive volume serial number, and I remember having to phone Xilinx's local office with the serial number.  Article: 20996 Subject: Re: ORCA 3T - input/output delay reduction? From: Peter Alfke <peter@xilinx.com> Date: Thu, 02 Mar 2000 11:14:33 -0800 Links: << >> << T >> << A >> I do not think the extra input delays are your problem. We ( i.e. Xilinx, but I suppose others do the same ) incorporate an extra delay in the input ( nowadays we make that programmable ) to compensate for the chip-internal clock delay. Without the extra data delay, the clock would arrive later than the data, which creates an ugly hold-time requirement on the data with respect to the external clock. These extra delays are of the order of 3 to <<10 ns on old and slow parts, hardly a problem for a 20 MHz system clock rate. Peter Alfke, Xilinx Applications ============================ Harald Simmler wrote: > Hi > > I have a design where 4 ORCA 3T125 chips communicate together > ( programmed in VHDL ). All four designs should run at arond 20 MHz. > At least the P&R tools calculates that frequency on internal delays. > > But the highest frequency on the board is only 8MHz. > The FPGAs are directly connected by wires, so I think that this > should not be the problem. I think that the PIO blocks which are > programmed as input add an delay block at the > input ( per default ? ) which has to be added to the internal > tPD. And the output is set to slow ( also per default ? ). > > Has anyone an idea what reduces the frequency and does anyone > know how to disable the input delay or change the settings for the PIO > blocks during P&R ( constrains in the CHDL code or in a constrains file > )?? > > Any help is needed. > Thanks in advance. > > H. Simmler > > -- > > --------------------------------------------------------------------------- > Harald Simmler Lehrstuhl fuer Informatik V > Universitaet Mannheim > Tel: +49-621-181-2632 ! NEW ! B6, 26 > Fax: +49-621-181-2634 ! NEW ! D-68131 Mannheim > eMail: simmler@ti.uni-mannheim.de Germany  Article: 20997 Subject: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic From: Edward Lee <edlee@seidcon.com> Date: Thu, 02 Mar 2000 11:24:21 -0800 Links: << >> << T >> << A >> They can also use clusters of FPGA to service the FPGA server, which in terms service other FPGA and FPGA servers. They can probably simulate nuclear explosion faster than the explosion itself, if the net is just million times faster! Andy Peters wrote: > Gary Cook wrote in message <38B4E75D.CAA624D7@sonyoxford.co.uk>... > > >"On-Line" arithmetic is a new form of arithmetic being tested at MIT > >I believe ... instead of writing complex and space consuming > >algorithms within FPGAs for functions such as sin/cos etc., the > >FPGA has a state machine that is programmed to generate ethernet > >packets that can be transmitted over the internet. They are sent, > >through an internet connection that the FPGA has access to, to a > >server somewhere that has enough grunts to be able to perform the > >requested arithmetic function very very quickly ... the result is returned > >back to the FPGA within a maximum time, but which is significantly > >less than the time it would have taken the fpga to perform it. In this > >way it is easy to envisage even more complex arithmetic functions > >being implemented, that have a deterministic response time. > >Of course, the server will typically only be performing arithmetic > >tasks, but if it's powerful enough it could serve many FPGA's > >thoeretically anywhere in the world ... even from space! It is > >possible, however, that due to internet congestion or packet > >misdirection, that the result that the FPGA is returned is not > >the expected arithmetic result, but the 1-800 telephone number of > >Delicous Debby Daring to Dabble in Delightful Doings .. rather > >confusing for the poor FPGA I wager .... > > > >... at least that's what I read in Electronics Times.... > > sounds like a clever method of extracting money from not-so-clever VCs! > > -- a > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul Stevens  Article: 20998 Subject: restrictions due to signal types of Global Clock inputs for Virtex From: gzs@clark.net (George) Date: Thu, 02 Mar 2000 19:54:19 GMT Links: << >> << T >> << A >>  I have a multi-clock design I am doing in a Virtex XCV1000 device. All four global clock inputs are used and the I/O bank where one of the clock inputs enters the chip is SSTL2. Xilinx tells me to make the clock be an SSTL2 signal. This is no problem. The FAE also tells me that I should not try to use this particular clock to clock any of the internal logic of the device, only the IO pads of the banks which are also SSTL2. This is very hard for me to believe. Does anyone know of any type of restriction on the uses of the global clocks depending on the Select IO types used for the clock inputs? Thanks. -George gzs@clark.net  Article: 20999 Subject: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ?? From: Ray Andraka <randraka@ids.net> Date: Thu, 02 Mar 2000 20:44:23 GMT Links: << >> << T >> << A >> Sounds like you have foundation 1.3 or 1.4. If you are going to do a serious design, I'd highly recommend you update the software. M1.3 and M1.4 were quite buggy, and were really a major step backwards from Xact6 in terms of functionality, reliability and speed (at least if you did any floorplanning). In my opinion, the first usable version of the M1 tools was 1.5i, before that there were way too many show stopper bugs. 2.1i is the current tool, and I hear rumors that 3.1 is due out very soon. 2.1i is a quantum leap in capability and speed over 1.5i. Also, they did away with the keying to the C drive serial number...I think it was too much a headache for product support. The licensing now uses a CD key similar to the microsoft stuff. As far as 2.1 being buggy, it's not if you are doing mainstream stuff. Go into the cobweb filled corners though, and I'll guarantee you'll find bugs. Virtually all the bugs I've found in it are either in the floorplanner or are in the mapper when run on floorplanned (RLOC'd) designs. I consider it a major bug when the mapper will not accept an RLOCed design with a legal layout, as it can prevent certain dense or high speed designs. I've got a customer on hold for one of these right now. You can get the student version of foundatin for$99.

Peter wrote:

> >I would go for Xilinx Foundation with FPGA Express - it won't cost
> >anything like \$15k. Also, I don't agree that Foundation 2.1i (with service
> >pack 5)
> >is really 'buggy'.
>
> I have a licensed copy in the office of versions 1.3 and 1.4 of the
> Xilinx successor to XACT, but at this moment can't remember its name -
> damn! Xilinx did a freebie on these to all XACT6 licensees. I wonder
> if this is relevant. I think it contains a primitive schematic entry
> program and maybe even a simulator. It locks to the C: drive volume
> serial number, and I remember having to phone Xilinx's local office
> with the serial number.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka