1994 Jul Aug Sep Oct Nov Dec 1994 1995 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1995 1996 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1996 1997 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1997 1998 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1998 1999 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1999 2000 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2000 2001 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2001 2002 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2002 2003 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2003 2004 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2004 2005 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2005 2006 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2006 2007 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2007 2008 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2008 2009 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2009 2010 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2010 2011 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2011 2012 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2012 2013 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2013 2014 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2014 2015 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2015 2016 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2016 2017 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2017 2018 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2018 2019 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2019 2020 Jan Feb Mar Apr May 2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

# Messages from 20300

Article: 20300
Subject: Re: Xilinx Tools
From: Keith Wootten <Keith@wootten.demon.co.uk>
Date: Fri, 4 Feb 2000 10:56:58 +0000
Links: << >>  << T >>  << A >>
In article <389aa14a.0@news1.cluster1.telinco.net>, David    Hawke
<dhawke@skynow.net> writes
>Keith,
>
>Get in touch with either MicroCall(now insight) or Avnet in the UK.
>
>F2.1i costs just $95 (DS-FND-BAS-PC) and the Vhdl/Vlog at$495
>(DS-FND-BSX-PC)
>
>Hope this helps,
>
>Dave Hawke
>Xilinx UK
>
>Keith Wootten wrote in message ...
>>Hi
>>
>>I've been using Foundation F1.4 for a while, using XC5215 and Spartan
>>XCS40.  I want to change to the 3.3V XCS40XL part, but my software won't
>>support this part.

[snip]

As I understand it, the two you suggest only support up to XC5210?

Cheers
--
Keith Wootten

Article: 20301
Subject: Re: Xilinx Tools
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Fri, 4 Feb 2000 08:46:38 -0600
Links: << >>  << T >>  << A >>
We should also point out that this is an ANNUAL cost.  The tool will not let
you start a new design after 1 year (unless you AGAIN pay the $95,$495, or
$2500 depending on the package. -- Keith F. Jasinski, Jr. kfjasins@execpc.com David Hawke <dhawke@skynow.net> wrote in message news:389aa14a.0@news1.cluster1.telinco.net... > Keith, > > Get in touch with either MicroCall(now insight) or Avnet in the UK. > > F2.1i costs just$95 (DS-FND-BAS-PC) and the Vhdl/Vlog at $495 > (DS-FND-BSX-PC) > > Hope this helps, > > Dave Hawke > Xilinx UK > > Keith Wootten wrote in message ... > >Hi > > > >I've been using Foundation F1.4 for a while, using XC5215 and Spartan > >XCS40. I want to change to the 3.3V XCS40XL part, but my software won't > >support this part. > > > >Apparently, there is no upgrade path for F1.4 and I'll have to *buy* > >some new software. To cope with both the XC5215 and the XCS40XL parts, > >I'll need to spend over GBP1000 - yes, one kilopound. I already spent > >over GBP2000 for the F1.4 stuff, and I'm not a volume user. > > > >Why do they do this? Surely the small company user has *some* value? > >The support from the dealer was poor and the promised training sessions > >never materialised once the money was paid, so cost of support is no > >justification. > > > >Can anyone recommend a UK dealer who is not a shark? > > > >Cheers > >-- > >Keith Wootten > >  Article: 20302 Subject: Re: Spartan 2 & Foundation From: Ray Andraka <randraka@ids.net> Date: Fri, 04 Feb 2000 15:20:23 GMT Links: << >> << T >> << A >> Sounds like you didn't select SpartanII as one of the devices to install during the installation procedure. I've had no problems doing a SpartanII design. Jean-Paul GOGLIO wrote: > Ray Andraka wrote <389A359A.2CBBEAA9@ids.net>... > >If you are not getting spartanII in the device list in the design manager, > >you either didn't install it or you didn't install it right. I think > >installing the spartan II requires a new CD code which you get from the > >Xilinx website. If you are still using your original CD key code, the > other > >stuff still works, but you won't see the SpartanII parts. Search on the > >Xilinx website for SpartanII and look for the installation instructions. > >IIRC, the procedure is spelled out in excruciating detail. You need SP4 > for > >the timings, and you need to go through the install procedure after > patching > >with SP4 to enable the spartanII (for that you also need the new key code). > > > >Nicolas Matringe wrote: > > > >> Hi > >> I am trying to implement a design in a Spartan 2 device. I (think I) > >> updated Foundation to enable these devices but I still don't manage to > >> do it. > >> When I want to synthesize (with FPGA Express) my design, I can not > >> choose the Spartan2 family (the family is not in the list). A Xilinx FAE > >> told me to choose Virtex family for synthesis and then Spartan2 for > >> mapping and P&R but I don't know where to do this. > >> If anyone can help... > >> Thanks in advance > >> > >> Nicolas MATRINGE DotCom S.A. > >> Conception electronique 16 rue du Moulin des Bruyeres > >> Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > >> Fax 00 33 1 46 67 51 01 FRANCE > > > >-- > >-Ray Andraka, P.E. > >President, the Andraka Consulting Group, Inc. > >401/884-7930 Fax 401/884-7950 > >email randraka@ids.net > >http://users.ids.net/~randraka > > > > > > Hi everybody, > > I have exactly the same problem with Foundation 2.1i sp4 when i try to > synthesize or to implement a design on a Spartan II. > 2 months a go, i got a new CD Key code from the xilinx website to use Virtex > E chips. > I have no trouble with making a synthesis / implementation on Virtex E > Chips. > 1 month a go, i tried to make a synthesis on Spartan II chips, this family > was not on the list. > I tried to get a new CD key code from the xilinx website to use Spartan II, > i got exactly the same code as the Virtex -E one. > I made a full unistallation / installation of Foundation, then of SP4 with > the new CD code, it still doesn't work. for Spartan II, and it still works > for Virtex E. > (I use Windows NT). > > What am i doing wrong ? > > J-P GOGLIO > GETRIS S.A. > 13 Chemin des Prés > 38240 Meylan > Tel : (33) 4 76 18 52 10 > Fax : (33) 4 76 18 52 01 > E-mail : goglio@getris.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka  Article: 20303 Subject: Re: Count 1's algorithm... From: Dragon <hyarbr01@NoSpam.harris.com> Date: Fri, 04 Feb 2000 10:35:21 -0500 Links: << >> << T >> << A >> If the problem is speed and/or area intensive, I approach this kind of problem by first examining the target architecture. If you are designing into a Xilinx 4000E architecture, you've got either 9 inputs and 1 output or 2 separate 4 inputs (one could be 5) and 2 separate outputs per CLB to work with. For example, if you had a 16 bit number whose bits you wanted to tally, here are some possible architectural solutions. 1. Count three 'ones' per CLB: With 2 sum bits you could count at most 3 ones. To count 16 ones you would need 5 CLBs and have one bit left over. Now you have five 2-bit numbers with one bit left over. If you add pairs of 2-bit numbers, you need 3 bits per sum. Since we have 3 pairs, we need 9 more CLBs. Now we have three 3-bit numbers. We can use 5 CLBs to add them together to get the five-bit result. This solution uses 19 CLBs with three levels of logic. 2. Use all 9 inputs per CLB: To count 9 ones we need a 4-bit result. In 4 CLBs we count the first 9 ones. In 3 CLBs we count the remaining 7. Now we have a 4-bit and a 3-bit number. Use 5 more CLBs to get the five-bit result. This solution uses 12 CLBs and two levels of logic. 3. Somewhere in the middle: With 2 sum bits you could count at most 3 ones. To count 16 ones you would need 5 CLBs and have one bit left over. Now you have five 2-bit numbers with one bit left over. Add three of the pairs of 2-bit numbers into a 4-bit sum. This would take 4 CLBs. Add the other two pairs and one left over bit into a 3-bit sum. This would take 3 CLBs. Use 5 more CLBs to get the five-bit result. This solution uses 17 CLBs and three levels of logic. Looks like solution 2 is the best way to go. If speed was not the issue, and you had access to a clock, I would go with Ray's suggestion of a shift reg and counter. Shift the bits and tap one stage to the clock enable of a 5-bit binary counter. That would need only 5 CLBs. - Craig Ray Andraka wrote: > The 'best' implementation for FPGAs depends on the amount of time you have to do > it and how many bits you are counting. > > For relatively small numbers of bits, use the 4LUTs to create partial sums of the > individual bits. the 4 LUT outputs will be weighted. YOu combine like weighted > outputs until you are down to 2 of every weight, then add those vectors together > in a conventional adder. That's a merged tree implementation. Note that most > merged tree work in the literature deals with gates with a fanin and fanout of > 2. The FPGA LUTs generally have a fan-in of 4, so for the most efficient merged > tree, you need to modify the approach slightly. > > For larger numbers of bits, you can take the odd bits, shift them down by one and > add them to the even bits. That will get you N/2 values of 0,1 or 2, but you get > to use the carry chain to cut down on the real-estate. Then take every other two > bit output, shift it down two bits and add to the even sets. Keep repeating that > till you have one set. > > If you have a clock that is n times faster than the data rate (not likely in your > case based on your problem statement), you can use a shift register and counter > (but that was obvious. huh?) > > "Pawe³ J. Rajda" wrote: > > > Does anyone has an idea how to quiclky count number of 1's (or 0's) > > in a word (i.e. 8 or 24 bits). I have to implement this as a part of > > algorithm in FPGA. > > > > -- > > Regards, > > Pawel J. Rajda > > > > ----------------------------------------------------------------------------- > > > > Pawel J. Rajda, MSc. E.E. mail: pjrajda@uci.agh.edu.pl > > Dept. of Electronic Engineering www: > > http://galaxy.uci.agh.edu.pl/~pjrajda > > AGH Technical University tel: (+48-12) 617 3980 > > Al. Mickiewicza 30 fax: (+48-12) 633 2398 > > 30-059 Cracow, POLAND > > ----------------------------------------------------------------------------- > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka  Article: 20304 Subject: OE in hierachial ABEL design From: "Georgi Beloev" <gbeloev@iname.com> Date: Fri, 4 Feb 2000 17:44:43 +0200 Links: << >> << T >> << A >> Hi, I am working on hierachial ABEL design using the Xilinx WebPACK tools. According to the documentation, connecting a lower-level tristate output to a higher-level pin results in the output enable being specified for the higher-level pin. However, the fitter stops with an error message: Logical Error 18823: Enable 'sd0.OE' is only allowed when top_level specified. What is the problem? Is there a special way to declare tristate outputs in higher-level sources? Thanks, -- georgi  Article: 20305 Subject: Re: Visualizing EDIF netlist for Xilinx From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> Date: Fri, 4 Feb 2000 08:45:49 -0700 Links: << >> << T >> << A >> Ernest Jamro wrote in message <38998E08.A189F4E5@uci.agh.edu.pl>... >> >> You have a schematic viewer in FPGA Express too (so in Fondation Express). > >Could you please let me know how to enter the schematic viewer program >in Foundation 2.1. Because I cannot find nothing like that. You get to the schematic viewer by running FPGA Express in "standalone" mode - not from within Project Manager. Exit outta Project Manager and look in your "Start" Menu item under Synopsys (unless you've changed that when you installed). After you synthesize and also after you optimize, if you right-click on the chip name, one of the options will be "view schematic." -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu Spelling Counts! You don't loose your money - you lose it.  Article: 20306 Subject: Re: Xilinx Tools From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> Date: Fri, 4 Feb 2000 08:47:02 -0700 Links: << >> << T >> << A >> Keith Jasinski, Jr. wrote in message ... >We should also point out that this is an ANNUAL cost. The tool will not let >you start a new design after 1 year (unless you AGAIN pay the$95, $495, or >$2500 depending on the package.

Maintenance here for the full-up Foundation tools is $995. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu Spelling Counts! You don't loose your money - you lose it.  Article: 20307 Subject: Conditional compilation in VHDL? From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca> Date: Fri, 04 Feb 2000 16:01:09 GMT Links: << >> << T >> << A >> Hi I am struggling to understand how I am supposed to debug VHDL code. How, for example, can I turn off part of the code. There are no block comments, no #ifdef's and #endif's as in C. I thought "generate" statement could do it but it seems that it's there for different purpose. So, how do you guys do this? Thanks, Mikhail Matusov  Article: 20308 Subject: Re: Xilinx Virtex Decoupling Cap Guidelines From: Rickman <spamgoeshere4@yahoo.com> Date: Fri, 04 Feb 2000 11:50:29 -0500 Links: << >> << T >> << A >> Allan Herriman wrote: > > On Thu, 03 Feb 2000 15:56:01 -0500, Rickman <spamgoeshere4@yahoo.com> > wrote: > Hey Rick, like what you say, except for the bit about the tantalum cap > needing to be near the power connector. It really doesn't matter > where it goes on the board. As you say, it's only effective at lower > frequencies. Also, its ESR will be much higher than the plane > impedance. > > Regards, > Allan. I would not argue the point of where to put the large value capacitor. But a rule of thumb is to put it near the power input. I assume this has to do with the resistance of the power distribution to the board, but I really don't know. Sometimes rules of thumb are not really very good. You should understand what is happening rather than to use rules blindly and this is one I don't understand. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com  Article: 20309 Subject: Re: Xilinx Virtex Decoupling Cap Guidelines From: Rickman <spamgoeshere4@yahoo.com> Date: Fri, 04 Feb 2000 11:53:56 -0500 Links: << >> << T >> << A >> Andreas Heiner wrote: > I would agree with your opinon. The app note is really stupid. If you would > place all the caps araound the device, you are not able to connect the > device, or you loose the bottom of the PCB. We're using Xilinx FPGA for a > long time (from XC4xxx up to XCV800) and we don't have had any problems with > it. The design of the PCB is more important than the cap's araound it. For > EMI-Problems not every time a lot of cap's are really good. A very good > solution is the use a wide band decoupling. The way for this is: > 1. Use multilayer PCB nboards with seperate power planes > 2. Create "island's" for the device > 3. calculate with the characteristics of the PCB (Er, distance of layer's, > etc.) the correct cap's for a wideband filter. I do not agree with this for the high freq caps. I feel that they need to be as close as possible to the chip pins. In fact I try to for a very short loop between a power pin and a ground pin with the cap. It may be a little overkill, but unless you know what your FPGA design is before you build the board, you can't estimate the high freq decoupling requirements. Also, what do you mean by creating an "island" for the device? Are you talking about the ground plane? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com  Article: 20310 Subject: Re: Conditional compilation in VHDL? From: eml@riverside-machines.com.NOSPAM Date: Fri, 04 Feb 2000 16:56:09 GMT Links: << >> << T >> << A >> On Fri, 04 Feb 2000 16:01:09 GMT, "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca> wrote: >Hi > >I am struggling to understand how I am supposed to debug VHDL code. How, for >example, can I turn off part of the code. There are no block comments, no >#ifdef's and #endif's as in C. I thought "generate" statement could do it >but it seems that it's there for different purpose. > >So, how do you guys do this? > >Thanks, >Mikhail Matusov 1) get a vhdl-aware editor. in emacs, for example, you can comment out an entire region with ^c^c - this does all the hard work for you. 2) if you know your tools, and you're not relying on a gui, use an external pre-processor, such as m4 or cpp 3) you can use a generate under some circumstances. the code inside a generate statement is always analysed, so it must be syntactically correct. if the condition is false, however, the code isn't elaborated, which is a later stage of the process. so, if your problem is an elaboration or run-time problem of some sort, rather than syntax, then the generate is useful. evan  Article: 20311 Subject: Re: Xilinx Virtex Decoupling Cap Guidelines From: Andreas Heiner <Andreas.Heiner@de.bosch.com> Date: Fri, 4 Feb 2000 18:38:11 +0100 Links: << >> << T >> << A >>  Rickman <spamgoeshere4@yahoo.com> schrieb in im Newsbeitrag: 389B0424.1E6385D5@yahoo.com... > Andreas Heiner wrote: > > I would agree with your opinon. The app note is really stupid. If you would > > place all the caps araound the device, you are not able to connect the > > device, or you loose the bottom of the PCB. We're using Xilinx FPGA for a > > long time (from XC4xxx up to XCV800) and we don't have had any problems with > > it. The design of the PCB is more important than the cap's araound it. For > > EMI-Problems not every time a lot of cap's are really good. A very good > > solution is the use a wide band decoupling. The way for this is: > > 1. Use multilayer PCB nboards with seperate power planes > > 2. Create "island's" for the device > > 3. calculate with the characteristics of the PCB (Er, distance of layer's, > > etc.) the correct cap's for a wideband filter. > > I do not agree with this for the high freq caps. I feel that they need > to be as close as possible to the chip pins. In fact I try to for a very > short loop between a power pin and a ground pin with the cap. It may be > a little overkill, but unless you know what your FPGA design is before > you build the board, you can't estimate the high freq decoupling > requirements. I had done the decoupling the same way. Put a cap as near as possible to the device. Well this works, but I've needed a lot of decoupling caps. With the wideband decoupling scheme it is not longer neccessary to place the cap's near to the devices. You will get a decoupling radius. All parts inside these radius are correctly decoupled. You can believe me that since using this scheme every board works fine and we have no problems anymore with our EMI tests. The theory of this wideband decoupling is really hard and I haven't understand it completly up to now. The decoupling works fine up to a frequency of 600-1000MHz. The maximum decoupling frequency depends on the size of the island's. > > Also, what do you mean by creating an "island" for the device? Are you > talking about the ground plane? No, the ground plane must be complete. Just the power planes will be seperated between the island. You just have small connections (depending on the power consumption inside the island). You have to seperate your board to some rectangular areas (this are the island's) and have to calculate the caps. The decoupling radius must conclude the whole area. If this is not possible, you have to change the seperation. Andreas Heiner  Article: 20312 Subject: Re: Spartan 2 & Foundation From: David Dye <davidd@xilinx.com> Date: Fri, 04 Feb 2000 10:41:05 -0700 Links: << >> << T >> << A >> Nicolas (and everyone), Spartan-II support through Foundation Express was not available until Foundation 2.1i Service Pack #5. This service pack includes data files and parts lists that upgrade both the HDL (Express) and Schematic flows through Foundation. http://www.xilinx.com/products/spartan2/ has everything you want to know about this new Xilinx FPGA family. Follow the links under "Software Support" for all the information about upgrading your Foundation software to support Spartan-II. thanks, david. David Dye Xilinx Technical Marketing Boulder, Colorado p.s. Nicolas, are you still having problems with RAM instantiation in Foundation Express that you reported on Monday? If so, our hotline should be able to help you out. Nicolas Matringe wrote: > Hi > I am trying to implement a design in a Spartan 2 device. I (think I) > updated Foundation to enable these devices but I still don't manage to > do it. > When I want to synthesize (with FPGA Express) my design, I can not > choose the Spartan2 family (the family is not in the list). A Xilinx FAE > told me to choose Virtex family for synthesis and then Spartan2 for > mapping and P&R but I don't know where to do this. > If anyone can help... > Thanks in advance > > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > Fax 00 33 1 46 67 51 01 FRANCE  Article: 20313 Subject: Re: Conditional compilation in VHDL? From: Mike Treseler <tres@tc.fluke.com> Date: Fri, 04 Feb 2000 10:01:41 -0800 Links: << >> << T >> << A >> Mikhail Matusov wrote: > > Hi > > I am struggling to understand how I am supposed to debug VHDL code. How, for > example, can I turn off part of the code. There are no block comments, no > #ifdef's and #endif's as in C. I thought "generate" statement could do it > but it seems that it's there for different purpose. > > So, how do you guys do this? I define some boolean constants and jump around them. -Mike Treseler  Article: 20314 Subject: Re: Xilinx Tools From: "David Hawke" <dhawke@skynow.net> Date: Fri, 4 Feb 2000 18:01:59 -0000 Links: << >> << T >> << A >> Keith, That is one slight caveat of the BAS systems. In my honest opinion you are better sticking with the 1.4 s/w for the 5200 devices, and doing any SpartanX, Virtex or SpartanII devices on the new s/w. That way you will not get penalised so heavily. Dave Hawke Xilinx UK Keith Wootten wrote in message ... >In article <389aa14a.0@news1.cluster1.telinco.net>, David Hawke ><dhawke@skynow.net> writes >>Keith, >> >>Get in touch with either MicroCall(now insight) or Avnet in the UK. >> >>F2.1i costs just$95 (DS-FND-BAS-PC) and the Vhdl/Vlog at $495 >>(DS-FND-BSX-PC) >> >>Hope this helps, >> >>Dave Hawke >>Xilinx UK >> >>Keith Wootten wrote in message ... >>>Hi >>> >>>I've been using Foundation F1.4 for a while, using XC5215 and Spartan >>>XCS40. I want to change to the 3.3V XCS40XL part, but my software won't >>>support this part. > >[snip] > >As I understand it, the two you suggest only support up to XC5210? > >Cheers >-- >Keith Wootten  Article: 20315 Subject: Re: Conditional compilation in VHDL? From: jakab tanko <jtanko@ics-ltd.com> Date: Fri, 04 Feb 2000 18:15:04 GMT Links: << >> << T >> << A >> Cut and paste, or just cut.....just kiddding of course... jakab Mikhail Matusov wrote: > Hi > > I am struggling to understand how I am supposed to debug VHDL code. How, for > example, can I turn off part of the code. There are no block comments, no > #ifdef's and #endif's as in C. I thought "generate" statement could do it > but it seems that it's there for different purpose. > > So, how do you guys do this? > > Thanks, > Mikhail Matusov  Article: 20316 Subject: Re: Conditional compilation in VHDL? From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca> Date: Fri, 04 Feb 2000 19:42:13 GMT Links: << >> << T >> << A >> Mike Treseler <tres@tc.fluke.com> wrote in message news:389B1405.8529A3F8@tc.fluke.com... > > I define some boolean constants and jump around them. Can you tell me please how exactly you are jumping? I am kinda missing a syntax book at the moment so I am not sure what kind of "goto" statement I could use... Generate statement as it was pointed out in another post requires code to be syntactically correct and what is worse I believe it works only inside of processes. If it is not generate then what is it? BTW is 'A Guide to VHDL Syntax' by J. Bhasker any good? I am looking at buying it from amazon.com or another e-trader but I would be happy to hear more opinions on this matter before I have spent money... Thanks, Mikhail Matusov  Article: 20317 Subject: Re: Conditional compilation in VHDL? From: Mike Treseler <tres@tc.fluke.com> Date: Fri, 04 Feb 2000 13:13:24 -0800 Links: << >> << T >> << A >> Mikhail Matusov wrote: > > Mike Treseler <tres@tc.fluke.com> wrote in message > news:389B1405.8529A3F8@tc.fluke.com... > > > > I define some boolean constants and jump around them. > > Can you tell me please how exactly you are jumping? I am kinda missing a > syntax book at the moment so I am not sure what kind of "goto" statement I > could use... By jumping around I meant using boolean constants as targets of if-then-else or case statements within a process to turn on or off synthesis or testbench options. > Generate statement as it was pointed out in another post > requires code to be syntactically correct I would suggest that you fix the syntax errors or comment them out. The simulation compiler is a very quick way to check syntax. If this is a tutorial exercise, I would suggest starting with a known good design and making small changes. -Mike Treseler  Article: 20318 Subject: Re: Which is the best HDL book ? From: elynum@my-deja.com Date: Fri, 04 Feb 2000 22:07:20 GMT Links: << >> << T >> << A >> In article <38978751.A9520A0A@flash.net>, davidtle@flash.net wrote: > Please help to give any info for the best verilog book for self-study. > > T.I.A > > Go to www.amazon.com and type in verilog and look up people's responses/critiques of books. Sent via Deja.com http://www.deja.com/ Before you buy.  Article: 20319 Subject: Re: Renoir problem: several engineers sharing a common setup? From: Phil Cole <pcole@net.com> Date: Fri, 04 Feb 2000 15:07:45 -0800 Links: << >> << T >> << A >> eml@riverside-machines.com.NOSPAM wrote: > > Thanks Phil - this is very useful. I've got a couple of other > questions, if you don't mind: > > >The way we did it was to have a template renoirPrefs > >which the designers copy to their local ~/.renoirPrefs > >(or the equivalent place for NT). renoirPrefs mostly > >controls generate styles, editor selection and other stuff > >users have their own dogmas about. Mistakes in renoirPrefs > >generally just prevent developers from proceeding with > >their task until they figure it out. The project is not > >messed with. We've never had to change renoirPrefs during > >the project. > > Some users want Renoir to control the downstream tools, so they'll be > putting simulator and synthesiser options (since each user also > generates a local EDIF) into their .renoirPrefs. As far as I can see, > this is going to make regression testing and building difficult, since > the master scripts must refer to everyone's individual .renoirPrefs. > It sounds like you don't have this problem, if individual .renoirPrefs > aren't source-controlled - is this right? You are right. We just provide a template that we know works. If users mess with their copy, the only effect is that they may not meet their schedule commitments if they don't know what they are doing. > > My inclination is not to allow Renoir to control any downstream tools. > I can write scripts that run Renoir in batch mode just to regenerate > any VHDL, but I can't see how user X, who wants Renoir to run his > flows, can fit into an overall automated project test or build. I can't either. If I'm doing my own work, I use Renoir to do little builds manually. There is a script which invokes renoir and the vhdl analyzer to do the big builds. It can do incremental builds, but we have more than a thousand source files in a full system, so it takes a while to find the one file that's out of date. We have another script which automates regressions. It compares test output files with a time stamp from the build script to determine which test cases are out of date. One project has well over 300 test cases, so we need this to keep track of them. > > >The renoir.ini (which contains the lib mappings mostly) > >is selected by setting the$RENOIRLIBS variable in each users
> >environment to the same value. Changing libraries around or adding them requires
> >the renoir.ini be checked out and changed by hand. This does
> >not happen often, and can usually be managed in a backward
> >compatible way.
> > <snipped>
> >e.g.
> >
> >[renoir_library]
> >lib_1   /source_control_file_system/$PROJECT/lib_1/renoir > >lib_2 /source_control_file_system/$PROJECT/lib_2/renoir
> >
> >[generated_library]
> >lib_1   $USER/objects/lib_1/vhdl.gen > >lib_2$USER/objects/lib_2/vhdl.gen
> >
> >[library]
> >lib_1   $USER/objects/lib_1/vhdl.lib > >lib_2$USER/objects/lib_2/vhdl.lib
>
> It sounds like:
>
> (a) you're keeping the working source libraries on the server, rather
> than checking them out into a local directory, and

Clearcase looks after the details, and spoofs the file system so all the
files look local. To get write permission, files must be checked out.
As far as the OS is concerned files are read only or not. Clearcase
looks after copying the checked in version into the users local space,
then accessing it.

I didn't want to complicate the explanation with the tricks clearcase
does. In fact, the generated files actually look like they sit in
directory trees right next to the source trees, with quite a lot of
interleaving. Individuals have their own "view" of the generated (private)
files. A file (or directory) of the same name can look completely different
in different views.
>
> (b) you're not keeping the generated libraries under source control,
> but simply regenerating as required - is this right?

Correct. As I said, Clearcase can arrange to share libraries since
it can figure out what object files depend on which source files,
and keep track of whether it already has a object which was generated
by a particular source configuration.

>
> Does \$RENOIRLIBS then point to a renoir.ini on the server?
Yes.
>
> It sounds like Clearcase is probably better than MKS. There's no
> pre-release/release mechanism; I think I'm going to have to bodge this
> by pre-releasing into an archive branch, testing, and then merging
> back onto the main trunk.

In HW we don't do branching. It hurts my brain too much, and we can do
what we need with labels.

When a developer thinks some code is ready, a pre-defined label (e.g.
PRE_RELEASE) is put on the new versions of all the files involved.

When it's time to release a new build:
1. Ask everyone to check in their good stuff and put the PRE_RELEASE
labels on the desired versions.

2. Set your configuration to select all the PRE_RELEASE versions.

3. Clean out the generated files and libs and rebuild.

4. Run the regression tests.

5. When the regressions pass, label all the source files with
labels PROJ_NAME_RELEASED and PROJ_NAME_RELxxxx where xxxx
is a release serial number.

Clearcase lets you set a config to select individual files by label or
branch/version number. So some files can be the labelled
release versions, some can be from a specific release, some can
be the latest (good for documentation when it's mixed with the
source files on the same server).

In general noone will be using the latest versions of any source
file, just the latest release. Of course they will be debugging
checked out versions of the files that they are working on.

Most source control systems I've seen can do labeled versions
and configurations.

Phil

Article: 20320
Subject: Re: Conditional compilation in VHDL?
From: Srinivasan Venkataramanan <venkataramanan.srinivasanNOveSPAM@philips.com.invalid>
Date: Fri, 04 Feb 2000 15:07:58 -0800
Links: << >>  << T >>  << A >>
Hello Mikhail,
I understand your point, having "block comments"
would be of Greate help for the designers, let's see if VHDL
committeee listens to us. For the moment, I think the
significant difference bet'n HDLs and S/W (like C) is a choice
of methodology before hand, either "top-down" or "bottom-up",
your leaf blocks, try and compile small blocks, and then glue
them together. This might give you a lot of files etc. But this
is how I do it.

Hope this helps a bit.

Regards,
Srini
>Mikhail Matusov wrote:
>>
>> Hi
>>
>> I am struggling to understand how I am supposed to debug VHDL
code. How, for
>> example, can I turn off part of the code. There are no block
>> #ifdef's and #endif's as in C. I thought "generate" statement
could do it
>> but it seems that it's there for different purpose.
>>
>> So, how do you guys do this?
>
>I define some boolean constants and jump around them.
>      -Mike Treseler
>
>

* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!


Article: 20321
Subject: Xilinx "WebCD" gripes
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Feb 2000 23:22:58 GMT
Links: << >>  << T >>  << A >>
Hey,  anyone else frustrated with the Xilinx webcd?  I liked the old
applinx format where they had recognizable names and file structure on
the disk (and PDF files).  It was nice because I could use it easily as
a databook without having to install extra stuff on the PC or having to
be online.  Today I went to look up device pinouts on the latest CD, and
it told me it was expired and forced me on-line.  Once online, it kept
getting data off the CD instead of the latest pages from the xilinx
website (for example, I couldn't get to the spartanII stuff on the web
site until I removed the CD).

Look Xilinx, If I want to go online to find the stuff, I don't want to
wrestle with the CD, and If I'm looking for something on the CD (like at
a customer's site), I don't want to have to go on line or use special
software to look it up.  Lets pick a format and stick with it.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20322
Subject: Re: Spartan 2 & Foundation
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Feb 2000 23:23:50 GMT
Links: << >>  << T >>  << A >>
For Alliance 2.1i it is service pack #4.  You sure there's a #5 for foundation?

David Dye wrote:

> Nicolas (and everyone),
>
> Spartan-II support through Foundation Express was not available until
> Foundation 2.1i Service Pack #5.  This service pack includes data files and
> parts lists that upgrade both the HDL (Express) and Schematic flows through
> Foundation.
>
> http://www.xilinx.com/products/spartan2/ has everything you want to know
> Support" for all the information about upgrading your Foundation software to
> support Spartan-II.
>
> thanks,
> david.
>
> David Dye
> Xilinx Technical Marketing
>
> p.s. Nicolas, are you still having problems with RAM instantiation in
> Foundation Express that you reported on Monday?  If so, our hotline should
> be able to help you out.
>
> Nicolas Matringe wrote:
>
> > Hi
> > I am trying to implement a design in a Spartan 2 device. I (think I)
> > updated Foundation to enable these devices but I still don't manage to
> > do it.
> > When I want to synthesize (with FPGA Express) my design, I can not
> > choose the Spartan2 family (the family is not in the list). A Xilinx FAE
> > told me to choose Virtex family for synthesis and then Spartan2 for
> > mapping and P&R but I don't know where to do this.
> > If anyone can help...
> > Thanks in advance
> >
> > Nicolas MATRINGE           DotCom S.A.
> > Conception electronique    16 rue du Moulin des Bruyeres
> > Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> > Fax 00 33 1 46 67 51 01    FRANCE

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20323
Subject: Re: Conditional compilation in VHDL?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Feb 2000 23:27:12 GMT
Links: << >>  << T >>  << A >>


Mikhail Matusov wrote:

> Mike Treseler <tres@tc.fluke.com> wrote in message
> news:389B1405.8529A3F8@tc.fluke.com...
> >
> > I define some boolean constants and jump around them.
>
> Can you tell me please how exactly you are jumping? I am kinda missing a
> syntax book at the moment so I am not sure what kind of "goto" statement I
> could use... Generate statement as it was pointed out in another post
> requires code to be syntactically correct and what is worse I believe it
> works only inside of processes. If it is not generate then what is it?

Generate works outside of processes.  It does have to syntactically correct.
I use the HDL editor inside the Aldec ActiveHDL.  With that you can select
many lines of text, then hit ctrl-K or right click to get a menu for
comment/uncomment the selected text.

>
>
> BTW is 'A Guide to VHDL Syntax' by J. Bhasker any good? I am looking at
> buying it from amazon.com or another e-trader but I would be happy to hear
> more opinions on this matter before I have spent money...
>
> Thanks,
> Mikhail Matusov

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20324
Subject: Re: Conditional compilation in VHDL?
From: dej@coup.inode.org (David Jones)
Date: Sat, 05 Feb 2000 00:42:55 GMT
Links: << >>  << T >>  << A >>
In article <389B1405.8529A3F8@tc.fluke.com>,
Mike Treseler  <tres@tc.fluke.com> wrote:
>Mikhail Matusov wrote:
>>
>> Hi
>>
>> I am struggling to understand how I am supposed to debug VHDL code. How, for
>> example, can I turn off part of the code. There are no block comments, no
>> #ifdef's and #endif's as in C. I thought "generate" statement could do it
>> but it seems that it's there for different purpose.

What is not well known is that generate can be used with "if":

if (SIZE = 2) generate
RESULT <= A and B;
end generate;

if (SIZE > 2) generate
ULO: MYBLOCK port map(
...
);
UHI: MYBLOCK port map(
...
);
RESULT <= ALO and BLO;
end generate;

You can actually define recursive logic this way.  ModelSim and Synopsys DC both
support it.  ModelSim may give you a warning that unresolved signals may have
multiple drivers, since it is not smart enough to realize that the two
conditionals will not be true at the same time, at compile time.