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Messages from 64475

Article: 64475
Subject: Re: How do I make use of local-clocks in a Virtex-2 FPGA?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Mon, 5 Jan 2004 10:41:15 -0800
Links: << >>  << T >>  << A >>
Please see ...

XAPP609 "Local Clocking Resources in Virtex-II Devices"
http://www.xilinx.com/bvdocs/appnotes/xapp609.pdf
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC


"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:btatdp$ifq$1@mawar.singnet.com.sg...
> Hi, there:
> I saw this statement in Virtex-2 datasheet, how do I make use of these
local
> clocks?
> Is there any documents on these local clocks?
>
> Best Regards,
> Kelvin
>
>
>
>
> Local Clocking
> In addition to global clocks, there are local clock resources
> in the Virtex-II devices. There are more than 72 local clocks
> in the Virtex-II family. These resources can be used for
> many different applications, including but not limited to
> memory interfaces. For example, even using only the left
> and right I/O banks, Virtex-II FPGAs can support up to 50
> local clocks for DDR SDRAM. These interfaces can operate
> beyond 200 MHz on Virtex-II devices.
>
>



Article: 64476
Subject: DCM Synthesis - Certify Planner Error
From: sateesh@ims.uni-hannover.de (Lagudu Sateesh)
Date: 5 Jan 2004 11:01:22 -0800
Links: << >>  << T >>  << A >>
Hello!!!

I am using DCM component (which is a ISE6.1 coregen synthesizable
module) in top level entity. This top level entity is to be ASIC
prototyped using Certify tool. During certify flow, compilation and
estimation of the flow is running smooth with out any errors. During
partitioning process, i assigned the DCM component and unassigned nets
( which are in 'system unassigned bin' of Partition tree view) to the
user FPGA U1. Then no unassigned components/instances are visible in
'system unassigned bin' of partition tree view. Then during synthesis
process, the following error occurs.

Running board compiler...
Board compiler completed

Board compiler: 0 errors, 0 warnings, 0 notes

Running job planner .....
Job: "Planner" terminated with error status: 3
See log file "~/rev_1/tst.srr"
All instances must be assigned before mapping.
Pleas view log file for a list of unassigned instances .

The .log file does not provide any unsigned instances. But it has
following messages.

Synplicity Planeer, version 6.2/3.2, Build 089R, built Jun 5 2003
nwrver.c:564 Error: vpn: Unknown format character 'ü'
Process took 0.523857 secs real time, 0.42 seconds cputime

Can any body suggest what was the error.

For your information, with out DCM component the entire certify
synthesis flow is perfect i.e. Compilation, estimation, partitioning
and synthesis.

Is the DCM output signals CLK0, CLKDV are depend on the derived clocks
from the synthesis process? If not, what is the bug?

Looking for your valuable suggestions

sateesh

Article: 64477
Subject: Altera CPLD - Illegal assignment-global clock
From: "J.F. FOURCADIER" <no_spam@wanadoo.fr>
Date: Mon, 5 Jan 2004 20:05:13 +0100
Links: << >>  << T >>  << A >>
Newbie

I try to use an Altera CPLD EPM7064. When I try to connect a register clock
input to a normal pin, I get the message "Illegal assignment-global
clock'input_clock' on pin 31.
I understand it's better to connect this kind of input on a dedicated clock
pin, but I cann't for wiring reasons.

The data sheet indicates a programmable register can be clocked by signals
from buried macrocells or I/O pins. How can I get this result ? I work on
the the graphic editor.

Thank you for your help !

Jean-François FOURCADIER,  F4DAY

website : http://perso.wanadoo.fr/jf.fourcadier/






Article: 64478
Subject: Re: 4-bit binary divider circuit PLEASE!!!!!!!
From: "Ken Taylor" <ken123@xtra.co.nz>
Date: Tue, 6 Jan 2004 08:27:33 +1300
Links: << >>  << T >>  << A >>
"Wing Fong Wong" <wing.fong.wong@ieee.org> wrote in message
news:btboms$lud$1@enyo.uwa.edu.au...
> In comp.arch.fpga Wouter van Ooijen (www.voti.nl) <wouter@voti.nl> wrote:
> >>If I were your prof, and I caught you blatantly trying to get others to
do your
> >>thinking for you, I'd make you design it using nothing but BC547's,
resistors
> >>and diodes. That way you might l-e-a-r-n something. That is why you are
at uni?
> >
> > Why would he need diodes?
> >
> >
> >
> > Wouter van Ooijen
> >
> > -- ------------------------------------
> > http://www.voti.nl
> > PICmicro chips, programmers, consulting
>
> That would be diode transitor resistor logic, stuff from 1st year
electronic
> engineering. Diode and resistors to make and gates and transitor
invertors.
> -- 
> Wing Wong.
> Webpage: http://wing.ucc.asn.au
>
You still don't need the diodes - it's wired-or logic.

Ken



Article: 64479
Subject: Re: is this a good idea
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 05 Jan 2004 19:35:28 GMT
Links: << >>  << T >>  << A >>
"Paul" <paulw@mmail.ath.cx> wrote in message
news:3ba4d769.0401050101.5f503a45@posting.google.com...
> "Jerry" <nospam@nowhere.com> wrote in message
news:<vvhf7ii29ntnbf@corp.supernews.com>...
> > "Paul" <paulw@mmail.ath.cx> wrote in message
> > news:3ba4d769.0401040319.40ffdbcd@posting.google.com...
> > > Hi
> > >
> > > I know that the "reg"'s are all zeroes when powered on (on Xilinx
> > > FPGAs). Is this a good idea (assumption) to work on? Can I assume the
> > > same for ASIC development? that is I don't have to change my codes
> > > later on?
> > >
> > > Thanks.
> >
> > Its the worst idea I have seen on this newsgroup to assume the state of
> > registers at power up in an ASIC.
> > BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption.
> > Watch your simulator. It should have unknown in registers that were not
> > initialized.
> > Some registers initial state is a don't care, some are very critical, it
all
> > depends on your design.
> >
> > Jer
>
>
> Can't I just tell the foundry that I need the regs to be zeroes at powered
on?
> Anyone done this before?

The foundary would have to use a special register primitive that is
supported by a power-on-reset mechanism added to your circuitry.  The ASIC
house would need a different netlist.  Do you want them doing some of your
design?

Also - MAJOR caveat:  the Xilinx devices do NOT always power up registers to
zero.  If the register is implemented with an FDS or FDSE primitive
(synchronous sets) the register powers up to a logic one.

As far as dedicated reset nets, Xilinx has warned many times in the past not
to rely on the dedicated net because the skew across the device - in older
devices, at least - could be large compared to the clock cycle.  The
suggestion in another post to synchronize your reset to each clock domain is
superb; releasing reset is usually an asynchronous event that can send only
some of your circuit out of reset on the first clock cycle.

I plan to use the BUFGMUX primitives to bring my FPGA with well-defined
power-on states into operation by enabling the clock to all elements at the
same time rather than rely on an asynchronous power-on reset OR explicit
snchonized resets to each and every friggin register, using significant
routing resources and some logic resources (by eliminating the synchronous
set/reset from my synthesizer's bag of tricks).  I would never parlay this
FPGA specific method to an ASIC.



Article: 64480
Subject: Re: Altera CPLD - Illegal assignment-global clock
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 05 Jan 2004 13:41:10 -0800
Links: << >>  << T >>  << A >>
J.F. FOURCADIER wrote:

> The data sheet indicates a programmable register can be clocked by signals
> from buried macrocells or I/O pins. How can I get this result ? I work on
> the the graphic editor.

On the 7064, the only route to the internal
clocks is through the special pins.

You may have to bend up a pin
and solder a wire.

     -- Mike Treseler


Article: 64481
Subject: Re: dynamic memory allocation NIOS
From: kempaj@yahoo.com (Jesse Kempa)
Date: 5 Jan 2004 13:49:24 -0800
Links: << >>  << T >>  << A >>
jwing23@hotmail.com (J-Wing) wrote in message news:<d6e7734d.0312302238.3dd6e6ff@posting.google.com>...
> i am using dynamic memory allocation to run in NIOS.
> i) this means using malloc to get the memory needed
> ii) and using free to free the memory needed
> 
> after testing, i think that the free function does not do anything. is
> there any way to free the memory allocated?

Hi J-Wing,

I have not had problems using malloc or free on Nios. I created the
following test code which shows malloc and free operating correctly.
Note that I am attempting to allocate slightly over 1MB of memory; in
this test I am only using SRAM on my Nios board, with is 1MB. If I
comment out the free(buff) line, malloc() will fail as the memory is
filled. When free(buff) is still in place, all malloc() operations
complete with success.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

===== Nios/malloc/free example code =====

#include "excalibur.h"

int main(void)
{
    int i=0, result=0, goodmallocs=0;
    unsigned char *buff;
    
    for(i=0; i< 1030; i++)
    {
        buff = (unsigned char *) malloc(1024);
        
        if(buff)
            goodmallocs++;
        else
            printf("error mallocing at i=%d\n", i);
            
        free(buff);
    }
    printf("I was able to malloc() %d 1024-byte blocks. Bye.\n",
goodmallocs);
    
    return 0;
}

=========================

Article: 64482
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: Ray Andraka <ray@andraka.com>
Date: Mon, 05 Jan 2004 16:55:17 -0500
Links: << >>  << T >>  << A >>
*bob, you are showing your age*

Bob Perlman wrote:

> On Thu, 1 Jan 2004 17:17:38 -0500, "Jerry" <nospam@nowhere.com> wrote:
>
> >WOW, your prof let you use NANDs? we had to do this using only
> >relays. Wish I had an easy prof like yours.
> >
> >(:>)
> >
> >Jer
>
> Hah! Luxury!  When I was a boy, Professor Babbage made us use gears
> and levers!  Compared to that experience, designing with today's EDA
> tools seems...well, pretty much the same, actually.
>
> Bob Perlman
> Cambrian Design Works

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 64483
Subject: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
From: ccon67@netscape.net (Marlboro)
Date: 5 Jan 2004 14:14:41 -0800
Links: << >>  << T >>  << A >>
kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>...
> Can anyone send me a 4-bit binary divider circuit in this email :
> kkaranasos@in.gr  ? I must make this homework for my university and i
> am late.
> I have to make this circuit only with NAND gates. 
> 
> PLEASE HELP !!!!!!!!!
> 
> Thanks a lot


divider? I think you've already known how to build  multiplier... make
one then turn it up side down, and voila you have divider.

Article: 64484
Subject: v2px70 available?
From: "T. Irmen" <tirmen@gmx.net>
Date: Mon, 5 Jan 2004 23:33:58 +0100
Links: << >>  << T >>  << A >>
Hi,

are they shipping?

Thomas



Article: 64485
Subject: Re: Newbie VHDL issue with CPLD
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 05 Jan 2004 14:48:11 -0800
Links: << >>  << T >>  << A >>
David T. wrote:

> I would appreciate a kick in the right direction.

 >    if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS
 > 	DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS

What does DAT_OUT(0) get when READ1 /= '1'  ?

       -- Mike Treseler



Article: 64486
Subject: Re: Altera CPLD - Illegal assignment-global clock
From: "Dejan Durdenic" <dejan.durdenic<remove_this>@zg.htnet.hr>
Date: Mon, 5 Jan 2004 23:50:24 +0100
Links: << >>  << T >>  << A >>
You have probably checked "Automatic Global Clock" in the "Global Project
Logic Synthesis"
window - that will assign your clock to the global clock input pin.Uncheck
it, and you can route
your clock where you like (although there will be a speed penalty, of
course).

- Dejan

"J.F. FOURCADIER" <no_spam@wanadoo.fr> wrote in message
news:btcch9$ge6$1@news-reader4.wanadoo.fr...
> Newbie
>
> I try to use an Altera CPLD EPM7064. When I try to connect a register
clock
> input to a normal pin, I get the message "Illegal assignment-global
> clock'input_clock' on pin 31.
> I understand it's better to connect this kind of input on a dedicated
clock
> pin, but I cann't for wiring reasons.
>
> The data sheet indicates a programmable register can be clocked by signals
> from buried macrocells or I/O pins. How can I get this result ? I work on
> the the graphic editor.
>
> Thank you for your help !
>
> Jean-François FOURCADIER,  F4DAY
>
> website : http://perso.wanadoo.fr/jf.fourcadier/
>
>
>
>
>



Article: 64487
Subject: Release of SPARK C-to-VHDL Parallelizing High Level Synthesis tool
From: gupt@hotmail.com (S Gupta)
Date: 5 Jan 2004 14:50:34 -0800
Links: << >>  << T >>  << A >>
We are pleased to announce the release of the SPARK parallelizing high-level
synthesis software tool developed at the Center for Embedded Computer Systems.
SPARK takes the behavior of an application specified in C as input
(with some restrictions) and produces register-transfer level (RTL) VHDL.
SPARK employs several parallelizing compiler, compiler, and high-level
synthesis transformations to generate a scheduled, resource bound data
path along with a FSM controller.  We have benchmarked SPARK on a range
of multimedia and image processing designs and also a case study with
an Intel design.

The download page is at:
http://www.cecs.uci.edu/~spark/download.shtml

This page has SPARK binaries for Solaris and Linux platforms, a User Manual,
and a Tutorial with a MPEG-1 player as an example.

See publications on the SPARK webpage for more details on our work:
http://www.cecs.uci.edu/~spark/publications.shtml

Sincerely

Sumit Gupta, Rajesh Gupta, Nikil Dutt, Alexandru Nicolau

http://www.cecs.uci.edu/~spark
Center for Embedded Computer Systems
University of California, Irvine and San Diego

************************************
Sumit Gupta
Post-Doctoral Researcher
Center for Embedded Computer Systems
University of California, Irvine

http://www.cecs.uci.edu/~sumitg
sumitg@cecs.uci.edu
************************************

Article: 64488
Subject: Re: Something additional: Adding internal signals in MODELSIM
From: Bassman59a@yahoo.com (Andy Peters)
Date: 5 Jan 2004 14:59:04 -0800
Links: << >>  << T >>  << A >>
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0401050612.5fce329a@posting.google.com>...
> Some additional question:
> Is the shown macro for functinal or for timing simulation ?
> The background of this question: When I run the simulation and
> open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
> I can find the original names of the primary inputs and outputs
> but I can NOT find the original internal names, these seem to be
> renamed by the compiler.
> If I want to analyse a state machine it is impossible without
> the original names.
> 
> So my question: How can I simulate (functional) without losing
> the original names ?

You do the functional simulation BEFORE you synthesize and place and
route.  Did you do that?

After place-and-route, did the static timing analyzer tell you that
you win?

--a

Article: 64489
Subject: fast mod (remainder) algorithm for V2?
From: "Brannon King" <bking@starbridgesystems.com>
Date: 05 Jan 2004 18:06:19 EST
Links: << >>  << T >>  << A >>
I'm looking for a fast integer mod routine to be executed on a Virtex2-6000.
Let's say 256bit unsigned integer divided by a 64bit unsigned integer where
I only care about the remainder. Any ideas or directions? I don't care how
many resources it uses. Thanks.



Article: 64490
Subject: Re: connecting tristates
From: Paulo Dutra <paulo@xilinx.com>
Date: Mon, 05 Jan 2004 15:43:09 -0800
Links: << >>  << T >>  << A >>
You can use SR 16636 as a starting point.
http://support.xilinx.com/techdocs/16636.htm

Once you have the INOUT port broken out to
the individual _T, _I, and _O ports in the MPD.

You can then assign these ports in the MHS.

BEGIN isa_gpio
PORT isa_sd_o =3D data_i
PORT isa_sd_i =3D data_o
END

BEGIN opb_gpio
PORT GPIO_I =3D data_i
PORT GPIO_O =3D data_o
END


Johan Bernsp=E5ng wrote:
> Hi,
>=20
> Currently I'm working on a OPB to ISA bridge to be included as a periph=
eral
> in a Microblaze system. To verify that the bridge works, I've also made=
 a
> GPIO that is connected as a peripheral on the ISA bus. The ISA data bus=
 is
> bidirectional and is thus implemented as a tristate port. Since the dat=
a
> port on the ISA GPIO also is bidirectional, that is also implemented as=
 a
> tristate. The problem is that when the two tristate signals are connect=
ed in
> the system.mhs file (data =3D isa_sd) XST interprets that to connect th=
e
> isa_sd_i with data_i, isa_sd_o with data_o, and isa_sd_t with data_t. I=
 have
> also tried to separate the data ports on the GPIO side, but I haven't w=
orked
> out how to specify that isa_sd_o should be connected to data_i and isa_=
sd_i
> to data_o.
>=20
> Does anyone with more experience on this matter than me have any good
> suggestions on how to solve the problem?
>=20
> Johan
>=20
>=20



--=20
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ `  Xilinx                              hotline@xilinx.com
/ /    2100 Logic Drive                    http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA


Article: 64491
Subject: Re: fast mod (remainder) algorithm for V2?
From: "Brannon King" <bking@starbridgesystems.com>
Date: 05 Jan 2004 19:35:31 EST
Links: << >>  << T >>  << A >>
In fact, I don't really care about the remainder other than it being
nonzero.

"Brannon King" <bking@starbridgesystems.com> wrote in message
news:btcqlb$722@dispatch.concentric.net...
> I'm looking for a fast integer mod routine to be executed on a
Virtex2-6000.
> Let's say 256bit unsigned integer divided by a 64bit unsigned integer
where
> I only care about the remainder. Any ideas or directions? I don't care how
> many resources it uses. Thanks.
>
>



Article: 64492
Subject: Re: Hyperthreading vs. Dual proc
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 06 Jan 2004 12:02:09 +1100
Links: << >>  << T >>  << A >>
On 05 Jan 2004 10:14:01 +0000, Martin Thompson
<martin.j.thompson@trw.com> wrote:

>Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:
>> 
>> The benefit of hyperthreading would be much more significant if there
>> was only a single processor, or if there were lots of threads running.
>> 
>
>I've found that enabling HT makes my machine useful for writing
>documentation, reading email and other non-demanding tasks whilst PAR
>is running.

It sounds like you have a single processor machine.  The differences
are much less obvious on a multi-processor machine, and certain things
(e.g. PAR) may be slower with hyperthreading enabled.

Regards,
Allan.

Article: 64493
Subject: Re: 4-bit binary divider circuit PLEASE!!!!!!!
From: YD <yd.techHAT@techie.com>
Date: Tue, 06 Jan 2004 00:10:30 -0200
Links: << >>  << T >>  << A >>
On Tue, 6 Jan 2004 08:27:33 +1300, "Ken Taylor" <ken123@xtra.co.nz>
wrote:

>"Wing Fong Wong" <wing.fong.wong@ieee.org> wrote in message
>news:btboms$lud$1@enyo.uwa.edu.au...
>> In comp.arch.fpga Wouter van Ooijen (www.voti.nl) <wouter@voti.nl> wrote:
>> >>If I were your prof, and I caught you blatantly trying to get others to
>do your
>> >>thinking for you, I'd make you design it using nothing but BC547's,
>resistors
>> >>and diodes. That way you might l-e-a-r-n something. That is why you are
>at uni?
>> >
>> > Why would he need diodes?
>> >
>> >
>> >
>> > Wouter van Ooijen
>> >
>> > -- ------------------------------------
>> > http://www.voti.nl
>> > PICmicro chips, programmers, consulting
>>
>> That would be diode transitor resistor logic, stuff from 1st year
>electronic
>> engineering. Diode and resistors to make and gates and transitor
>invertors.
>> -- 
>> Wing Wong.
>> Webpage: http://wing.ucc.asn.au
>>
>You still don't need the diodes - it's wired-or logic.
>
>Ken
>

But the OP wanted to use only NAND gates. Oh well, an inverter on each
input will turn an OR to a NAND, and as we're already spending
transistors by the bucket might as well go for it.

- YD.

-- 
Remove HAT if replying by mail.

Article: 64494
Subject: Re: Xilinx Logicore PCI64 Problem
From: kanglc@starhub.net.sg (owner)
Date: 5 Jan 2004 18:19:29 -0800
Links: << >>  << T >>  << A >>
Thanks for all your replies.

Mark,

Mark Schellhorn <mark@seawaynetworks.com> wrote in message news:<lMhKb.1496$k_.366272@news20.bellglobal.com>...
> It sounds like either:
> 
> a) You have changed one or more instance names within the design hierarchy so 
> that the paths 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' etc. are not valid, or

No, I have not modify the core's vhd files at all. In fact, take this
example above, the instance PCI-AD64 does not even exists. The "higher"
hierarchy instances - PCI_CORE/PCI_LC/ are correct. What I found is
an instance named PCI_AD64_IO31_OFD of a xilinx macro called X_FF
used under the component PCI_LC.

> b) You have allowed the synthesis tool to change the design hierarchy by 
> flattening or grouping modules.
> 
> In my design I used the keep_hierachy XST synthesis attribute to tell XST to 
> leave the PCI core hierarchy alone when flattening my logic. I also did a 
> search/replace on the UCF file to change some instance names in the path so that 
> they match the instance names I wanted to use in my design.
> 
>      Mark

May be I should try XST first, using the ping example,
as suggested by Xilinx.

Thanks.

Regards,
LC

Article: 64495
Subject: Followup to those that downloaded SeaHDL/SimHDL
From: joe@nospam.com (joe)
Date: Tue, 6 Jan 2004 03:37:28 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello to the folks that downloaded SeaHDL/SimHDL from 
http://etherdesign.tripod.com.   Please tell me your first impressions.  The 
product is still in Beta so let us know if you ran into any 'show stopper' 
bugs, etc.  Does it look like the product might be helpful solving a particular 
problem, etc?  We just got our new rev out which allows the user to create 
custom primitives for the Simulator.

Thanks for any feedback!  etherdesign@mailcity.com



Article: 64496
Subject: Re: Something additional: Adding internal signals in MODELSIM
From: ALuPin@web.de (ALuPin)
Date: 5 Jan 2004 23:08:57 -0800
Links: << >>  << T >>  << A >>
Hi,

that is the question !
In Altera QuartusII software there is 
--> Processing  ----> Start Compilation and Simulation

But when starting Modelsim the internal names (I gave the different
signals) are not used anymore with the exception of the inputs
and outputs. 
Maybe I should mention that I used megafunctions (RAM structures ... that
I instantiated). But nevertheless the inputs of these megafunctions
should be shown, but they are not!

Andrés

> 
> You do the functional simulation BEFORE you synthesize and place and
> route.  Did you do that?
> 
> After place-and-route, did the static timing analyzer tell you that
> you win?
> 
> --a

Article: 64497
Subject: Where i can get the programming sequence of CoolRunner?
From: shang77_03@yahoo.com (chi)
Date: 5 Jan 2004 23:34:56 -0800
Links: << >>  << T >>  << A >>
Hello,

Can anyone help me to get the programming sequence of CoolRunner CPLD
to program through boundary-scan pins?

Regards,
chi

Article: 64498
Subject: XST cant compile with blaxkboxes.
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Tue, 6 Jan 2004 15:37:10 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am using ISE6.1 in office and ISE6.1Webpack at home. Both have service
park 3 I think.

How come on Webpack, I can synthesize with XST and instantiate black boxes
at top level,
however in original ISE6.1 it gave me error, complaining the that it can't
find the bm_4b_v2...
The bm_4b_v2 is in the same running directory.

ERROR:HDLCompilers:87 - ../hdl/top_bt.v line 487 Could not find
module/primitive 'bm_4b_v2'

Is there any settings for XST to read in NMC macros as blackboxes?

Could anybody teach me how to handle this situation?

Best Regards,
Kelvin




Article: 64499
(removed)




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